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Data transfer between BASYS 2 and Python

Jed Brody

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This is a Python question more than an FPGA question, but maybe someone on this forum can help.

I have 15 BASYS 2 boards in my instructional lab.  I'd like students to be able transfer data between the FPGA and a computer, and then process the data (not just observe in it Digilent Adept Register I/O).  I have one PmodUSBUART, which works well, but I'd rather not buy 14 more of them.

With DPIMREF.VHD (https://reference.digilentinc.com/_media/reference/software/adept/adept-2/dpimref_programmers_manual.pdf) on the FPGA, I can transfer data over the USB using Digilent Adept.  We teach Python in our department, so what I'd really like is Python code that can do Register I/O like Adept does. I tried http://www.delajii.net/mmWiKi/articles:dpcutil.py but without success.  (My various attempts and resulting error messages are too numerous to list.)  I'd appreciate any suggestions.  Thanks.

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@Jed Brody,

This is a good and wonderful question!  It hits on some fundamental details/parts of an FPGA and FPGA design, specifically that you need some means of getting feedback from within the FPGA regarding what the FPGA is doing ... some way to know if it is working, or if not why not.

I'm not sure if Digilent offers an official solution, but I do have a C++ program together with some Verilog RTL that can be used to command a wishbone bus within any FPGA that can support an 8-bit interface (such as a UART).  You can then place onto that wishbone bus ... whatever registers you wish to place there.  The C++ interface to this approach is described here--it's pretty simple.  I've now used this approach for a XuLA2-LX25 project, a Basys-3 project, a CMod-S6 project, and now I'm using it for an Arty project.

The underlying transfer mechanism and encoding was at one time very simple: Commands and responses are sent to the bus in 36-bit word groups (six bytes, where only 64 printable values are used).  The top four bits of these word groups is decoded into one of a couple of commands 1) set the address for a subsequent operation, 2) write data to the current address and increment the address, 3) write data without incrementing the address, and 4) read from the (previously set) address.  Responses similarly use 36-bit words.  Well, that was how it started.  I then added some repeat-value compression.  I also added special return code words to indicate things like: 1) the interface was idle, 2) an "interrupt" had taken place on the FPGA, 3) a "bus error" had taken place, 4) the bus had reset itself, 5) a piece of data had been written (an acknowledgement), etc.

If you are interested in this approach, we can have a longer discussion about it.  It is entirely open source and GPLv3, so ... let me know if this would help.


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