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Transfer of data from PS to PL in Zynq 702 SoC



I am working with the ZYnq 7020 Soc and i am new to working with this board. In my project I want to transfer the data from Zynq PS section to PL section. I am unable to find how to do it by searching on internet.suggest me by providing any reference design/manual to achieve this communication.

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I think the best solution would be to make your own custom AXI IP with some registers that the processor can modify. Here is a guide


Another idea would to be to look at the FIFO IP and see if you can leverage the AXIS interface to your advantage.




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Dear @sLowe,

I just tumbled to this post while I was searching for an answer to my question.


I have a design including a 16-bits counter inplemented on a Zedboard with CLG484 FPGA. I want to send the outputs of my counter to UART via processor and see them in the SDK output in TeraTerm. I could successfully achieve the turorials in the following links:



and I successfully see the output value stored in the simple_register on TeraTerm via SDK tool.

Now, I want to add this design to my own design in order to send the output of counter to the simple register or directly to the output to see it in TeraTerm. The problem is that once I add the processor in my top file, it does not recognize it as a component !!! Can you please guide me where it the problem? Notice that I cannot employ PlanAHead for my design since I am using Vivado2017.1 and I have some routing constraints written in XDC file that are not recognized and importable in PlanAhead since it uses the UCF file !!!

I am stucked at this phase !:(


Thanks and Regards,

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