(very) beginner question

[engrpetero]

I must have missed that day in class.  Sometimes (often?) when I look at example verilog code, I'll see statements like shown in the code snip below.  My understanding (through reading and in practice) is that all of these samples show valid ways to set the registers to 0 or in the case of test2, to 5, and the difference is in readability (or to get a point across considering the vector).  Am I wrong?

 

reg 		test1;
reg [3:0]	test2;

// set to 0
test1 <= 0;
test2 <= 2'b00;
test2 <= 0;
          
// set to 5
test2 <= 4'b0101;
test2 <= 4'h5;
test2 <= 5;

 

[artvvb]

@engrpetero

The "raw" 0s and 5s are "unsized constants" and evaluate as 32 bits wide. There are edge cases where it can matter, particularly when working with larger buses. The line test2 <= 2'b00 would imply zero-padding up to four bits for test2[2] and test2[3]. There are also some implications on whether these right-hand-side constants are treated as signed or unsigned. If you can get your hands on a copy of the Verilog language standard, it should define how this all works.

For the specific examples you show, there are no functional differences. It just gets weird when using constants in larger expressions. One of the places where VHDL requiring explicit type conversion (while also a headache) can be pretty nice.

[engrpetero]

Thanks for the response.  I sometimes see a mixture of these things in the same code samples and usually just pass it off as readability or ease of understanding.  The 'evaluate as 32 bits wide' comment is certainly a useful one as is the comment about potentially being treated as signed or unsigned.

I'll find a copy of the standard and see if I can glean anything else.

When I am using constants, particularly with large numbers, I often find a base 10 representation to be easier to visualize (so 10000 instead of 0x2710).  If I'm masking something off, I often use 4'b1100 instead of 4'hC as I think it is easier to visualize the intent.