About weird FMS3818KRC DAC of Virtex-II Pro

[mopplayer]

Hi all,

It seems not work as expected as datasheet described as follows:

If I just assign the G5~G0 (linked to G7~G2 pin) according to EDK plb_tft_cntlr_ref_v1_00_d pcore (Digilent VGA example, tft_clk DCM 25MHz) :

reg [10:0] CounterX;
reg [8:0] CounterY;
wire CounterXmaxed = (CounterX==767);

always @(posedge tft_clk)
if(CounterXmaxed)
  CounterX <= 0;
else
  CounterX <= CounterX + 1;

always @(posedge tft_clk)
if(CounterXmaxed)
    CounterY <= CounterY + 1;
     
reg vga_HS, vga_VS;
always @(posedge tft_clk)
begin
  vga_HS <= (CounterX[9:4]==0);   // active for 16 clocks
  vga_VS <= (CounterY==0);   // active for 768 clocks
end

assign HSYNC_i = ~vga_HS;
assign VSYNC_i = ~vga_VS;

always @(posedge tft_clk) begin
    if (SYS_plbReset) begin
        G0_i <= 1'b0;
        G1_i <= 1'b0;
        G2_i <= 1'b0;
        G3_i <= 1'b0;
        G4_i <= 1'b0;
        G5_i <= 1'b0;
    end else begin
        G0_i <= 1'b1;
        G1_i <= 1'b1;
        G2_i <= 1'b1;
        G3_i <= 1'b1;
        G4_i <= 1'b1;
        G5_i <= 1'b1;    
    end        
end

Sys_plbReset = 1 released in a short time, so it should be a whole green screen, but I only got a black 640x480 screen. It was not matching that datasheet, but any demo bitstreams would show screen properly.

if I changed to just like this, I could get partial green screen:

always @(posedge tft_clk) begin
    if (SYS_plbReset) begin
        G0_i <= 1'b0;
        G1_i <= 1'b0;
        G2_i <= 1'b0;
        G3_i <= 1'b0;
        G4_i <= 1'b0;
        G5_i <= 1'b0;
    end else begin
        G0_i <= ~(CounterX[9]);
        G1_i <= ~(CounterX[9]);
        G2_i <= ~(CounterX[9]);
        G3_i <= ~(CounterX[9]);
        G4_i <= ~(CounterX[9]);
        G5_i <= ~(CounterX[9]);    
    end        
end

 

When I changed G5 like this:

always @(posedge tft_clk) begin
    if (SYS_plbReset) begin
        G0_i <= 1'b0;
        G1_i <= 1'b0;
        G2_i <= 1'b0;
        G3_i <= 1'b0;
        G4_i <= 1'b0;
        G5_i <= 1'b0;
    end else begin
        G0_i <= ~(CounterX[9]);
        G1_i <= ~(CounterX[9]);
        G2_i <= ~(CounterX[9]);
        G3_i <= ~(CounterX[9]);
        G4_i <= ~(CounterX[9]);
        G5_i <= (CounterX[9]);    
    end        
end

I got a black screen again. It seems that’s not expected as the datasheet. Conflicts? Is there any documented detail?

What's the method of Digilent to handle this chip at that time?  
Didn’t FMS3818KRC always catch the input value?

Any help would be appreciated.

Edited 16 hours ago by mopplayer

[artvvb]

Hey,

Unfortunately the Virtex II Pro has been EOL for some time, so we may not be able to help much. That being said, some of the details of the source you've quoted seems odd to me, mostly in that the counters roll over at X=767 and Y=511, rather than X=799 and Y=524, as standard for 640x480@60 Hz. VGA Signal 640 x 480 @ 60 Hz Industry standard timing (tinyvga.com). If you're pulling this from example code on the site, could you send a link to the full source?

Thanks,

Arthur

[mopplayer]

Hi artvvb,

It's more likely associated with triple video DAC, not FPGA and boards self problem, so we have better to figure out those issues.

Nowadays ADV7123 should face the same issue, I think.

 

The simple test source came from fpga4fun and Digilent EDK pcore.
767 X 511 and standard 799 X 524 is no different, but I have modified it.

I have done more tests, because Hsync and Vsync are independent of DAC, but the VGA port monitor will detect all the signals. So if I put the DAC with G0~G7, B0~B7, R0~R7 as 1 on the front porch or back porch, the result would be unexpected. I was surprised about the VGA D-SUB standard, HDMI would result in a different way on the same monitor. I had not touched the old VGA standard in the past.

Any help would be appreciated.

plb_tft_cntlr_ref.zip

Edited 29 minutes ago by mopplayer