Pmod Kypd

[nitdawg]

Hi,

I am new at this and bought a basys 3 dev board with 5 Pmod boards. I am trying to play around with the Pmodkypd and on digilent site they have some sample code to try (VHDL). The decoder file is attached. On line 40 it states signal sclk(19:0), what is it's purpose? I wish the example code had more comments describing its function for beginners like me.

Decoder.vhd

[artvvb]

Hi @nitdawg

Welcome to the Forum.

The sclk signal is a counter used to schedule when the column outputs are updated and when the row inputs are read back and decoded. Since it's reset after reaching 0b01100001101010001000 (~400,000), and the input clock is 100 MHz (which has a 10 ns period), the entire loop takes about 4 ms, as indicated in some of the comments in the file. The main reason to do this scheduling is to let the signals output from the FPGA propagate through the KYPD circuitry and settle before inputs are read back. Millisecond timing between changes in which columns are selected may have been chosen (as opposed to running the loop much faster) so that the module acts somewhat like a debouncer, without requiring additional logic to detect and ignore bouncy edges - the drawback here is that it will likely miss quick taps of a button.

Hope this helps,

Arthur