Connecting Pmod DA2 to Zybo Z7

[Toinou]

Hi, I need to connect a pmod da2 to my Zybo Z7, i found a lot of code but don't really understand how to use them.

I did a vhdl code to generate a sine wave and send it to the pmod da2 to see it on a external oscilloscope.

You can find the VHDL code here SinGen.vhd

I use also the Pmod reference found there and did a top module to connect them.DA2RefComp.vhdTopModule.vhd

I don't really understand where my problem is 

[Viktor Nikolov]

Have you simulated the design? That is the only way to know for sure what is happening. 🙂

I believe you know you need to drive input signals RST and START properly. From the source code of DA2RefComp.vhd, I have an impression that it requires rst='1' for at least one clock to initialize the internal signals properly.

[Toinou]

I did a simulation to test 2 conversion.

It seems to work pretty well, I get in D1 and D2 a correct value, I just can't understand how to drive the Start signal, as in my constraints files I assigned RST to a simple Push button, should I also assign START to a push button, but this means that everytime I want to convert I need to push a button. This is a strange way and not really realistic way to do it, can you give me more explanation on this ?

 

[Viktor Nikolov]

In general, it is very usual for an HDL module to have reset and enable signals as its input. In your case, the enable signal is called "start."
In some scenarios, you do not want the module logic to run all the time; hence, you have an enable signal to start/stop the module's logic.

If I understand you well, you want the logic to start producing the output right after the power-up.
I think that you shouldn't have RST and START as external signals (i.e., connected to buttons or pins on the board). Keep them internal to the TopModule and implement a simple state machine in the TopModule, which will assert RST for one clock cycle and then assert START.

[Toinou]

Thanks you my DAC is now working fine!
My initial goal was to connect an ADC and a DAC to my fpga, so I did a Top with the adc and dac connected to see if I can send for exampe a Square wave but when I do it in real life I have the output which is divided by 2. Like if I send 2V i get 1V.

Here is my whole code do you have any idea from where this could come from ?

 

TopModule.vhd pmod_adc_ad7476a.vhd spi_master_dual_miso.vhd DA2RefComp.vhd

[Viktor Nikolov]

Maybe the culprit for factor of 2 difference are these lines in the pmod_adc_ad7476a.vhd:

adc_0_data <= spi_rx_data_0(12 DOWNTO 1); --assign channel 0 ADC data bits to output        
adc_1_data <= spi_rx_data_1(12 DOWNTO 1); --assign channel 1 ADC data bits to output

I would expect "(11 DOWNTO 0)".

I see no apparent reasons for bit shifting output from the ADC. The serial interface diagram in the ADC's datasheet doesn't show any special meaning of the lowest bit. But I may be missing something. I suggest using in HW debugging to see what the actual values coming from the ADC are.

Edited August 30 by Viktor Nikolov