Arty A7 Ethernet

[yash]

Hello, im pretty new to the FPGA world, and want to setup a communication between my PC and my arty A7 board over ehternet, but i am having too many errors at each step. I followed the step by step tutorial provided by digilent, but still ended up failing at bitstream generation.  
Can anyone help by providing a good source? 
I am stuck at building the block design to setup an ethernet itself. 
Above mentioned tutotial - https://digilent.com/reference/learn/programmable-logic/tutorials/arty-getting-started-with-microblaze-servers/start
Error at bitstream generation - [DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are system_i/clk_wiz_0/inst/clk_out1.
 

[JColvin]

Hi @yash,

That particular guide is in the process of being updated.

What I have done to get Ethernet working on the Arty A7 was to follow this guide, https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi, to get an initial block design (main difference from the old style being that the clocking is done from the MIG with the 25 MHz reference clock from the Clocking Wizard now being downstream of that) and then adding in the Ethernet materials from the guide you referenced.  The resulting block design should look something like the pdf I attached for the 2023.1 project I made.

I also uploaded a Vitis export that sets up the built in Xilinx Echo Server; instructions for how to import it can be found in demos that use Vitis/SDK such as this one: https://digilent.com/reference/programmable-logic/arty-z7/demos/hdmi-input.

Let me know if you have any questions.

Thanks,
JColvin

design_1.pdf vitis_export_archiveAA35EchoServer20231.ide.zip

[yash]

9 hours ago, JColvin said:

Hi @yash,

That particular guide is in the process of being updated.

What I have done to get Ethernet working on the Arty A7 was to follow this guide, https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi, to get an initial block design (main difference from the old style being that the clocking is done from the MIG with the 25 MHz reference clock from the Clocking Wizard now being downstream of that) and then adding in the Ethernet materials from the guide you referenced.  The resulting block design should look something like the pdf I attached for the 2023.1 project I made.

I also uploaded a Vitis export that sets up the built in Xilinx Echo Server; instructions for how to import it can be found in demos that use Vitis/SDK such as this one: https://digilent.com/reference/programmable-logic/arty-z7/demos/hdmi-input.

Let me know if you have any questions.

Thanks,
JColvin

design_1.pdf 93.12 kB · 0 downloads vitis_export_archiveAA35EchoServer20231.ide.zip 9.35 MB · 0 downloads

Thanks alot @JColvin! 
I will give this a try soon. Currently im trying to flash my c program on the non-volatile memory of arty a7, if you have any tips /guide for it, it'd be really appreciated.
Thank you again
Yash