kevin vannorsdel Posted June 18 Share Posted June 18 Hello, I guess I am wondering if the Digital Discovery Logic Analyzer capability has a state analyzer mode wherein the data is read in on a user supplied clock rather than an internal sampling clock? Thoughts? Link to comment Share on other sites More sharing options...
0 attila Posted June 18 Share Posted June 18 Hi @kevin vannorsdel Digital Discovery supports Sync capture mode in which the trigger detector module is used for sample condition, level and/or edge. Triggering can't be used in this mode. Analog Discovery 3, ADP2230, ADP3X50 support external reference clock and sampling on a clock in Oscilloscope interface where Digital channels can also be enabled, Logic Analyzer embedded in Scope. Link to comment Share on other sites More sharing options...
0 kevin vannorsdel Posted June 18 Author Share Posted June 18 Thanks! So if we use this sync capture mode it will sort of free-run trigger-wise -- right? Meaning... there wont be a way to begin sampling the data on a particular condition? That is probably ok. How long is the FIFO (?) or in other words, lets say we feed in a clock at 10MHz and use sync capture mode, how much data can the DD take in before it fills up? I hope these questions make sense. Thank you very much. Link to comment Share on other sites More sharing options...
0 attila Posted June 18 Share Posted June 18 yes, yes, The device buffer is 256MiB, 256M samples @ 8bit, 128M @ 16bit, 64M @ 32bit, 32M @ 48b. The sync capture uses data streaming, so with custom application the length is unlimited. Link to comment Share on other sites More sharing options...
0 kevin vannorsdel Posted June 24 Author Share Posted June 24 HI @attila, would you be able to clarify or get me started in a decent direction on how we would set this up using API functions? It's a little difficult (so far) for me to understand which functions in teh WaveFroms SDK Reference Manual apply to DigitalDiscovery vs other products... Link to comment Share on other sites More sharing options...
0 kevin vannorsdel Posted June 24 Author Share Posted June 24 I found digitalin_sync.py that seems helpful. Still trying to understand how to specify which pins are sampled in ... in sync mode. I presume it is set with DigitalInSampleFormatSet() ? Link to comment Share on other sites More sharing options...
0 attila Posted June 26 Share Posted June 26 Hi @kevin vannorsdel Yes, DigitalIn_Sync.py is similar to the WaveForms application Sync mode See: Link to comment Share on other sites More sharing options...
0 kevin vannorsdel Posted June 26 Author Share Posted June 26 HI @attila, does this mean that for format=8 it actually clocks in 16 bits- DIN[7-0] AND DIO[31-24] ? Link to comment Share on other sites More sharing options...
0 attila Posted June 26 Share Posted June 26 8bit format stores 8 DIOs or DINs, 16bit -> 16, 32bit -> 32, 64bit -> all 48 channels With FDwfDigitalInInputOrderSet 0 the samples bits represent: 8bit DIN[7:0], 16bit DIN[15:0], 32bit DIO[31:24]DIN[23:0], 64bit DIO[39:24]DIN[23:0] with 1: 8bit DIO[31:24], 16bit DIO[39:24], 32bit DIN[15:0]DIO[39:24], 64bit DIN[23:0]DIO[39:24] Link to comment Share on other sites More sharing options...
Question
kevin vannorsdel
Hello, I guess I am wondering if the Digital Discovery Logic Analyzer capability has a state analyzer mode wherein the data is read in on a user supplied clock rather than an internal sampling clock?
Thoughts?
Link to comment
Share on other sites
8 answers to this question
Recommended Posts
Create an account or sign in to comment
You need to be a member in order to leave a comment
Create an account
Sign up for a new account in our community. It's easy!
Register a new accountSign in
Already have an account? Sign in here.
Sign In Now