CMOD A7-35T PCB Layout files.

[Will Creek]

My Company is looking at the CMOD A7-35T as a way to drive an evaluation board and give our customers an FPGA reference design to use with our custom IC.

The problem is that we need 1.8V 800Mbps+ DDR signals. We need both input and output signals. All of the CMOD IO pins are 3.3V

Looking at the schematic of the CMOD and the PCB it looks almost impossible to reconnect the IO banks to 1.8V instead of 3.3V. The power pin connections are internal to the PCB. Also, it would be easy to modify the 3.3V supply to 1.8V with a resistor change, but the onboard SRAM and EEPROM will not work at 1.8V.

So, we are forced to lay out our own version of the board. We have a schematic, but would have to create a PCB layout. 
We only need 50 - 100 boards, so it will probably cost more to make our own than buy them, but it's that or use the competitor's FPGA.

Two questions:
Is the schematic complete? I am particularly concerned about the EEPROM and bootstrap circuitry.
Can we get a layout file of the PCB to save us some time? We would of course sign NDAs promising not to sell it.

The last question is in the category of "it doesn't hurt to ask".

I see that others have asked the IO voltage question before. There are not many 3.3V applications left outside of the hobby world. If you are looking for a cheap project modification to sell a lot more boards, programmable voltage IO banks feels like a great opportunity. Upgrade the RAM to DDR3 while you are at it.

Of course the real reason to have evaluation boards is to really show off the FPGA parts. The Artix 7 family is seriously hobbled by only being able to evaluate it with an IO standard from the last century.

Edited June 15 by Will Creek
error

[D@n]

Quote

The problem is that we need 1.8V 800Mbps+ DDR signals.

Yeah, that's going to require a new PCB design.

Quote

Is the schematic complete? I am particularly concerned about the EEPROM and bootstrap circuitry.

Digilent has routinely kept the configuration related portions of their schematics proprietary.  At one time this information was proprietary to Xilinx IIRC. Since then, Xilinx has released the details of the protocol--so all is not lost.  If you know where to look, the information you need can be found elsewhere.  FTDI provides examples.  Intel/Altera provide examples.  Other Xilinx boards have examples--just not DIgilent.  If you struggle to find what you need, I know Digilent has entertained the idea of people purchasing this information from them.

My personal challenge with the 3.3V boards is that 1) there are so many 3.3V peripherals/PMods out there, 2) I'm not sure I've seen the rest of the world agree on whether the next standard should be 1.8V, 1.5V, 1.35V, or 1.2V.  Many projects I've been on require several voltage standards, depending upon which part is being accessed.  3) Worse, some parts like SD-Cards want you to start out at 3.3V and then switch to a lower voltage.  So, while 3.3V may be an ancient standard, it's still more of a workable standard than many of the lower voltages have become.

Dan

[JColvin]

Hi @Will Creek,

Regarding the PCB layout (as noted by D@n, Digilent has made the decision not to have that part of our schematic be publicly available), I have personally not heard of this request being granted since I've been at Digilent, but like you said it doesn't hurt to ask, so I have sent you a PM for a contact you can reach out to to pitch your request.

Thanks,
JColvin

[Will Creek]

Thanks for responding. We have made the decision to go with a different option, but we will keep this in mind for future products.

Will

[D@n]

@JColvin,

I've always assumed that enough $$ would grease the skids sufficiently ... feel free to clarify if this is not the case.

Dan

[JColvin]

Anecdotally, as I am not involved in this process so I could be wrong, I've really only heard of a single instance of the PCB materials being shared, but that detail is over 5 years old at time of writing.

Conversely, I do know that Digilent is open to customized/OEM requests (PLTW being an example). I personally do not have any insight on the MOQ, process, or timeline associated with such requests, but can connect any interested party with the correct Digilent contact.

Thanks,
JColvin