how can I reach the memory on audio demo project with zybo z7 10 ?

[taha]

I completed the audio demo part its running but I could not find the how I can reach memory in the code.

demo.c demo.h

[Viktor Nikolov]

Looking at the code of the demo I see that the DMA transfer is done to the address MEM_BASE_ADDR, which is a macro defined in demo.h.

See this line #383 in audio/audio.c:

uTransferVariable.l = XAxiDma_SimpleTransfer(&AxiDma,(u32) MEM_BASE_ADDR, 5*u32NrSamples, XAXIDMA_DEVICE_TO_DMA);

I don't know what is the format of audio samples. Let's assume it's u16. Then I would access the memory like this: 

u16 *AudioData = (u16*) MEM_BASE_ADDR;

u16 TenthAudioSample = AudioData[9];

 

[artvvb]

Viktor is correct, you can access the data using the buffer base address. The audio samples are 24-bit samples 0-padded up to 32 bits (the top eight bits are zeros). On review of the VHDL sources (https://github.com/Digilent/Zybo-Z7-HW/blob/20/DMA/master/repo/local/ip/d_axi_i2s_audio_v2_0/src/i2s_ctl.vhd), I'm not clear on how the left/right channels are packed - they alternate, as is standard for I2S, but I'm unclear on whether one or the other is guaranteed to be the first in the buffer.

Within the 24-bit field, data is twos-complement signed (I2S standard). Assuming the left channel is always first, this means:

u32 *AudioData = (u32*) MEM_BASE_ADDR;

u32 FirstRawSampleLeftChannel = AudioData[0];
u32 FirstRawSampleRightChannel = AudioData[1];
u32 SecondRawSampleLeftChannel = AudioData[2];
u32 SecondRawSampleRightChannel = AudioData[3];
// and so on...

int FirstSampleLeftChannel = (AudioData[0] & 0x800000) ? (-(int)((~AudioData[0]+1) & 0xffffff)) : (AudioData[0]);
// tested with python expression: raw_to_int = lambda raw: raw if (raw & (1 << 23)) == 0 else -(((~raw+1) & 0xffffff)+1)