Any device that can be used as a SPI master at 100 MHz in 1.8V logic?

[thomas1998]

Hello friendly people on the forum,

I am wondering if there is any FPGA/MCU product that can be used as a SPI master and communicate with slaves at 100MHz in 1.8V logic. I was looking at Arty Z7 featuring zynq 7000 but that one can only output 3.3V logic (correct me if i m wrong).
Thanks for the help in advance.

Best,
Thomas

[dpaul]

@thomas1998

As far as I know, you can set multiple FPGA GPIO pins to 1.8V or 3.3V.

You can use the Vivado GUI or use TCL commands to specify the pin constraints.

So in principle you can choose any FPGA, implement SPI Master on the FPGA, set the SPI ports to GPIO 1.8V and connect it with a SPI Slave.

[Viktor Nikolov]

The circuitry surrounding the FPGA chip defines the voltage used by GPIO pins (i.e., the board provides power to the GPIO banks). It is not just a setting in the constraints file.

The Digilent boards I know have fixed voltage on the GPIO pins.

I experimented with the Avnet MicroZed board. This board needs to be connected to a carrier card for it to be useful. You can design the carrier card to supply the voltage you need to the GPIO pin banks. I describe the details in this article.

Nevertheless, if you use a level shifter, you can use a Digilent 3.3 V board with a 1.8 V peripheral for testing. For example, on my carrier card described in the article, I'm using TXB0108 (rated for 100 MHz) to shift from 3.3 V to 5 V. But TXB0108 can also be used for shifting from 3.3 V to 1.8 V.
You should also be able to find ready-to-use breakout boards with level shifters on the market.

Edited May 27 by Viktor Nikolov
added info about level shifters

[dpaul]

Really?

For Digilent boards, is it not possible to choose the FPGA GPIO pins to either 1.8V or 3.3V operation as per the designer's wish (using Vivado GUI or TCL)?

Please enlighten me.

[D@n]

There are several Digilent boards having an FMC port, with an adjustable voltage bus.  I personally have the Nexys Video.  While the voltage cannot be adjusted while running, it can be set at configuration time and held fixed.

[dpaul]

5 hours ago, D@n said:

 While the voltage cannot be adjusted while running, it can be set at configuration time and held fixed.

Yes that's what I meant, after the FPGA loads the bitstream and the design is running, the GPIO pin voltages are fixed to either 1.8V or 3.3V  as long as the bitstream is running and the board is not powered off.

I think that is what the OP @thomas1998 wants to do!

Edited May 28 by dpaul

[Viktor Nikolov]

I wasn't aware of FMC port. Thanks, @D@n, for pointing this out.

Nevertheless, when I look into the Nexys Video Reference Manual, it seems that the FMC port voltage can and must be set dynamically by PL logic during runtime.

Quote

An FPGA design can dynamically change the VADJ voltage to suit a certain FMC mezzanine card or application. Care must be taken to disable the regulator first by bringing “VADJ_EN” low, setting “SET_VADJ(1:0)” and enabling the regulator again. Please note that for proper voltage levels in digital signals connected to VADJ-powered FPGA banks (ex. user push-buttons), the correct I/O standard still needs to be set in the design user constraints (XDC or UCF file). See the schematic and/or the constraints file to determine which signals are in VADJ-powered banks. The provided master UCF and XDC files assume the default VADJ voltage of 1.2V, declaring LVCMOS12 as the I/O standard for these signals.

 

[D@n]

@Viktor Nikolov,

What you are missing is the fact that the IO standards used when building a design (i.e. a .bit file) are fixed for that design (.bit file).  To switch IO standards, you have to reconfigure the logic (i.e. load a new .bit file).  You can't change IO standards on the fly by adjusting a GPIO pin.  I mean ... you can change voltages on the fly, but not the IO standard those pins are connected to and so you are essentially forced to reconfigure to switch voltages.

Dan

[thomas1998]

On 5/28/2024 at 3:37 AM, dpaul said:

Yes that's what I meant, after the FPGA loads the bitstream and the design is running, the GPIO pin voltages are fixed to either 1.8V or 3.3V  as long as the bitstream is running and the board is not powered off.

I think that is what the OP @thomas1998 wants to do!

@dpaulThanks Paul. It is exactly what i wanted. I thought this thread was dead after two days of silence and i only think of checking on this now. thanks a lot for the replies.

Edited June 3 by thomas1998

[dpaul]

@thomas1998 Thank you! Please mark it as a solution it has solved your problem.

I am not very regular in these forums.