How can I evaluate the data transmission status and observe the internal cache flow of a Vitis project?

[Mamatchai]

Hello,

As title, I'm currently working on an AMP (Asymmetric Multiprocessing) mode project. In this project, one core (CPU0) processes the data received from ZmodADC1410 and stores it in DDR3, which is a shared resource between the two cores. The other core (CPU1) establishes a TCP connection and acts as both client and server to continuously transmit the data stored in DDR3 to the server. However, I noticed that the sampling rate of our ZmodADC1410 is 40 Mbps,so according to the calculation based on the network speed requirement, it would be 40M*28 (dual-channel) = 1120Mbps, while the fastest network speed is only 160 Mbps. In theory, this should cause either bottlenecking or packet loss, but my senior has implemented a UDP version of the project without encountering such issues. The transmission is continuous and normal. Therefore, I want to examine the internal data transmission status and observe the hardware's cache flow.I wonder if there is any tools or method that I can acheive this.

Edited May 8 by Mamatchai

[Ionel]

TCP awaits for acknowledged before sending the next package while UDP does not. Therefor you can loose data via UDP. If that is not a concern it is ok. Even if there is such a tool, how do you connect such a tool the PS cache?