Jump to content
  • 0

How can I evaluate the data transmission status and observe the internal cache flow of a Vitis project?


Mamatchai

Question

Posted (edited)

Hello,

As title, I'm currently working on an AMP (Asymmetric Multiprocessing) mode project. In this project, one core (CPU0) processes the data received from ZmodADC1410 and stores it in DDR3, which is a shared resource between the two cores. The other core (CPU1) establishes a TCP connection and acts as both client and server to continuously transmit the data stored in DDR3 to the server. However, I noticed that the sampling rate of our ZmodADC1410 is 40 Mbps,so according to the calculation based on the network speed requirement, it would be 40M*28 (dual-channel) = 1120Mbps, while the fastest network speed is only 160 Mbps. In theory, this should cause either bottlenecking or packet loss, but my senior has implemented a UDP version of the project without encountering such issues. The transmission is continuous and normal. Therefore, I want to examine the internal data transmission status and observe the hardware's cache flow.I wonder if there is any tools or method that I can acheive this.

Edited by Mamatchai
Link to comment
Share on other sites

0 answers to this question

Recommended Posts

There have been no answers to this question yet

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now
×
×
  • Create New...