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Simulation of the Arty Z7-10 with DDR in VIVADO




I'm trying to do a project that PL can read/wrtie DDR3 with High performance AXI interface of ZYNQ on my Arty Z7-10, and I want to know is there an IP for the DDR IS43TR16256A-125KBL(which is the DDR3 used in Arty Z7-10) so I can simulate my design with HDL wrapper on vivado.

Since  I don't find this kind of resource that can used for simulation on https://www.issi.com/US/Index.shtml

If anyone know where to find it, it will be a lot of help for me, thanks.



Edited by wayyu
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You can use the DDR3 Control IP core provided by Xilinx.

The Ip is free to use.

Using the GUI of the IP you can select AXI as the user_interface for the Ctrl Core.

There is also the Ctrl IP core documentation, MUST read it. Also there is an example_design in there which you MUST try out before creating your custom design.

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