Cascaded Halfband Filter

[Shaq]

module Hf_Filter(clk, hf1_clk, rst_n, input_data, counter, hf1_output, output_data, hf2_clk, hf3_clk, hf2_output);

    parameter N = 16;
    
    input hf1_clk, clk, rst_n, hf2_clk, hf3_clk;
    input [N-1:0] input_data;
    output reg [N-1:0] output_data, hf1_output, hf2_output;
    output reg [7:0] counter;
    
    
    always@(posedge clk or posedge rst_n)
        begin
            if (rst_n == 1)
                counter <= 8'b0;
            else
                counter <= counter + 1;
        end
    
    
    // Define states
    typedef enum logic [3:0] {
        STATE_IDLE,
        STATE_HF1,
        STATE_HF2,
        STATE_HF3
    } state_t;
    
    // Declare state and next state variables
        state_t state, next_state;
        

always @ (posedge clk or posedge rst_n) begin
    if (rst_n == 1) begin
        state <= STATE_IDLE;
    end else begin
        state <= next_state;
    end
end

always @( * )  begin
    // Default next state is current state
    next_state = state;
    
    // State transitions
    case (state)
        STATE_IDLE: begin
            if (counter == 0) begin
                next_state = STATE_HF1;
            end
        end
        
        STATE_HF1: begin
            if (counter == 2) begin
                next_state = STATE_HF2;
            end
        end
        
        STATE_HF2: begin
            if (counter == 4) begin
                next_state = STATE_HF3;
            end
        end
        
        STATE_HF3: begin
            if (counter == 8) begin
                next_state = STATE_IDLE;
            end
        end
    endcase
end
    

    //Instantiate the three halfband filters
     
       Hf_Filter1 Hf_Filter1_inst (.input_data(input_data), .hf1_clk(hf1_clk), .rst_n(rst_n), .hf1_output(hf1_output));
        Hf_Filter2 Hf_Filter2_inst (.input_data(hf1_output), .hf2_clk(hf2_clk), .rst_n(rst_n), .hf2_output(hf2_output));
        Hf_Filter3 Hf_Filter3_inst (.input_data(hf2_output), .hf3_clk(hf3_clk), .rst_n(rst_n), .output_data(output_data));
    
endmodule 

module Hf_Filter1(
    input hf1_clk,         // Clock input
    input rst_n,       // Reset input (active high)
    input [15:0] input_data, // Input sample (16-bit)
    output reg [15:0] hf1_output // Filter output
);
    parameter N = 16;

    // Halfband filter coefficients 
                                
                                
    wire [N-1:0] w0 = 16'b1010100010111110;
    wire [N-1:0] w1 = 16'b0010011011000001;
    wire [N-1:0] w2 = 16'b1010100011100010;
    wire [N-1:0] w3 = 16'b0010101101110110;
    wire [N-1:0] w4 = 16'b1010111010010100;
    wire [N-1:0] w5 = 16'b0011010100010011;
    wire [N-1:0] w6 = 16'b0011110000000000;
    wire [N-1:0] w7 = 16'b0011010100010011;
    wire [N-1:0] w8 = 16'b1010111010010100;
    wire [N-1:0] w9 = 16'b0010101101110110;
    wire [N-1:0] w10 = 16'b1010100011100010;
    wire [N-1:0] w11 = 16'b0010011011000001;
    wire [N-1:0] w12 = 16'b1010100010111110;
    
    wire [N-1:0] B_in, B_out;
    
    Buffer Buffer (.clk(clk), .rst_n(rst_n), .B_in(B_in), .B_out(B_out));
    
    
    //Multiplication
    wire [N-1:0] mul0, mul1, mul2, mul3, mul4, mul5, mul6, mul7, mul8, mul9, mul10, mul11, mul12;
    
    
    assign mul0 = input_data * w0;
    assign mul1 = B_out * w1;
    assign mul2 = (B_out + B_out) * w2;
    assign mul3 = (B_out + B_out + B_out) * w3;
    assign mul4 = (B_out + B_out + B_out + B_out) * w4;
    assign mul5 = (B_out + B_out + B_out + B_out + B_out) * w5;
    assign mul6 = (B_out + B_out + B_out + B_out + B_out + B_out) * w6;
    assign mul7 = (B_out + B_out + B_out + B_out + B_out + B_out + B_out) * w7;
    assign mul8 = (B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out) * w8;
    assign mul9 = (B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out) * w9;
    assign mul10 = (B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out) * w10;
    assign mul11 = (B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out) * w11;
    assign mul12 = (B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out) * w12;

    
    //Addition Operation
    
    wire [N-1:0] sum; 
    assign sum = mul0 + mul1 + mul2 + mul3 + mul4 + mul5 + mul6 + mul7 + mul8 + mul9 + mul10 + mul11 + mul12;
    
    always@(posedge hf1_clk or posedge rst_n)
    begin if (rst_n == 1) begin
        hf1_output <= 16'b0;
        end
        else begin
        hf1_output <= sum;
        end
    end
    
endmodule 

module Buffer(
    input wire clk, // Clock input
    input wire rst_n, // Reset input (active low)
    input wire [15:0] B_in, // Input signal
    output wire [15:0] B_out // Output signal
);
    wire [15:0] inv1_out;
    wire [15:0] inv2_out;

    // First inverter
    assign inv1_out = ~B_in;

    // Second inverter (acts as a delay)
    assign inv2_out = ~inv1_out;

    // Output
    assign B_out = inv2_out;

   
endmodule

module Hf_Filter2(
    input hf2_clk,         // Clock input
    input rst_n,       // Reset input (active high)
    input [15:0] input_data, // Input sample (16-bit)
    output reg [15:0] hf2_output// Filter output
);
    parameter N = 16;

    // Halfband filter coefficients 
                                
                                
    wire [N-1:0] w0 = 16'b1010100010111110;
    wire [N-1:0] w1 = 16'b0010011011000001;
    wire [N-1:0] w2 = 16'b1010100011100010;
    wire [N-1:0] w3 = 16'b0010101101110110;
    wire [N-1:0] w4 = 16'b1010111010010100;
    wire [N-1:0] w5 = 16'b0011010100010011;
    wire [N-1:0] w6 = 16'b0011110000000000;
    wire [N-1:0] w7 = 16'b0011010100010011;
    wire [N-1:0] w8 = 16'b1010111010010100;
    wire [N-1:0] w9 = 16'b0010101101110110;
    wire [N-1:0] w10 = 16'b1010100011100010;
    wire [N-1:0] w11 = 16'b0010011011000001;
    wire [N-1:0] w12 = 16'b1010100010111110;
    
    wire [N-1:0] B_in, B_out;
    
    Buffer Buffer (.clk(clk), .rst_n(rst_n), .B_in(B_in), .B_out(B_out));
    
    
    //Multiplication
    wire [N-1:0] mul0, mul1, mul2, mul3, mul4, mul5, mul6, mul7, mul8, mul9, mul10, mul11, mul12;
    
    
    assign mul0 = input_data * w0;
    assign mul1 = B_out * w1;
    assign mul2 = (B_out + B_out) * w2;
    assign mul3 = (B_out + B_out + B_out) * w3;
    assign mul4 = (B_out + B_out + B_out + B_out) * w4;
    assign mul5 = (B_out + B_out + B_out + B_out + B_out) * w5;
    assign mul6 = (B_out + B_out + B_out + B_out + B_out + B_out) * w6;
    assign mul7 = (B_out + B_out + B_out + B_out + B_out + B_out + B_out) * w7;
    assign mul8 = (B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out) * w8;
    assign mul9 = (B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out) * w9;
    assign mul10 = (B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out) * w10;
    assign mul11 = (B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out) * w11;
    assign mul12 = (B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out) * w12;

    
    //Addition Operation
    
    wire [N-1:0] sum; 
    assign sum = mul0 + mul1 + mul2 + mul3 + mul4 + mul5 + mul6 + mul7 + mul8 + mul9 + mul10 + mul11 + mul12;
    
    always@(posedge hf2_clk or posedge rst_n)
    begin if (rst_n == 1) begin
        hf2_output <= 16'b0;
        end
        else begin
        hf2_output <= sum;
        end
    end
    
endmodule 

module Hf_Filter3(
    input hf3_clk,         // Clock input
    input rst_n,       // Reset input (active high)
    input [15:0] input_data, // Input sample (16-bit)
    output reg [15:0] output_data// Filter output
);
    parameter N = 16;

    // Halfband filter coefficients 
                                
                                
    wire [N-1:0] w0 = 16'b1010100010111110;
    wire [N-1:0] w1 = 16'b0010011011000001;
    wire [N-1:0] w2 = 16'b1010100011100010;
    wire [N-1:0] w3 = 16'b0010101101110110;
    wire [N-1:0] w4 = 16'b1010111010010100;
    wire [N-1:0] w5 = 16'b0011010100010011;
    wire [N-1:0] w6 = 16'b0011110000000000;
    wire [N-1:0] w7 = 16'b0011010100010011;
    wire [N-1:0] w8 = 16'b1010111010010100;
    wire [N-1:0] w9 = 16'b0010101101110110;
    wire [N-1:0] w10 = 16'b1010100011100010;
    wire [N-1:0] w11 = 16'b0010011011000001;
    wire [N-1:0] w12 = 16'b1010100010111110;
    
    wire [N-1:0] B_in, B_out;
    
    Buffer Buffer (.clk(clk), .rst_n(rst_n), .B_in(B_in), .B_out(B_out));
    
    
    //Multiplication
    wire [N-1:0] mul0, mul1, mul2, mul3, mul4, mul5, mul6, mul7, mul8, mul9, mul10, mul11, mul12;
    
    
    assign mul0 = input_data * w0;
    assign mul1 = B_out * w1;
    assign mul2 = (B_out + B_out) * w2;
    assign mul3 = (B_out + B_out + B_out) * w3;
    assign mul4 = (B_out + B_out + B_out + B_out) * w4;
    assign mul5 = (B_out + B_out + B_out + B_out + B_out) * w5;
    assign mul6 = (B_out + B_out + B_out + B_out + B_out + B_out) * w6;
    assign mul7 = (B_out + B_out + B_out + B_out + B_out + B_out + B_out) * w7;
    assign mul8 = (B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out) * w8;
    assign mul9 = (B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out) * w9;
    assign mul10 = (B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out) * w10;
    assign mul11 = (B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out) * w11;
    assign mul12 = (B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out + B_out) * w12;

    
    //Addition Operation
    
    wire [N-1:0] sum; 
    assign sum = mul0 + mul1 + mul2 + mul3 + mul4 + mul5 + mul6 + mul7 + mul8 + mul9 + mul10 + mul11 + mul12;
    
    always@(posedge hf3_clk or posedge rst_n)
    begin if (rst_n == 1) begin
        output_data <= 16'b0;
        end
        else begin
        output_data <= sum;
        end
    end
    
endmodule 

This is my code and the output when I simulate it in modelsim is xxxxxxx or unknown. 

[artvvb]

Hi @Shaq

Welcome to the forum.

Digilent doesn't support ModelSim. That said, if this is the top module in your simulation, you likely need a testbench and some kind of stimulus to apply to your module's input ports.

Thanks,

Arthur