Signal Generation through DDS and analyzing the generated signal through FFT IP core in Vivado

[amna]

I'm trying to generate signal of 1MHz by using DDS IP block at clock frequency of 100MHz but at output the time period of one cycle of generated sine wave is 10us which means wave of 10MHz is generated. Further more when I took the FFT of signal then the obtained output is shown as below. Can you guide me what is wrong with DDS and FFT IP core output. I am attaching the screenshot of block diagram and output. 

Edited March 14 by shop magic

[artvvb]

Hi @amna

Could you provide the settings of your DDS compiler? The more IP settings provided the better, to make it easier to reproduce your results. I'm also assuming your results are in simulation?

Thanks,

Arthur

[amna]

On 3/14/2024 at 12:45 PM, artvvb said:

Hi @amna

Could you provide the settings of your DDS compiler? The more IP settings provided the better, to make it easier to reproduce your results. I'm also assuming your results are in simulation?

Thanks,

Arthur

Greetings @artvvb..

The IP settings of DDS compiler are done as below:

Yes the results are in simulation.

Regards,

Amna

Edited March 19 by amna

[amna]

Hi @artvvb.

I hope you are doing fine. I am looking forward for the response of the question. Thank you

[artvvb]

Apologies for the delay. I haven't been successful in reproducing your setup. Some additional settings that might help are 1. the constant values applied to the CONFIG interface of the XFFT IP - I assume the tlast port is tied to a constant one. 2. XFFT settings - both the Configuration and Implementation tabs include settings that affect what values are provided to the CONFIG interface.

I'd also be curious about why the XFFT S_AXIS_DATA interface's tlast port seems not to be connected - in simulation, not asserting tlast at the expected time causes the XFFT core to assert either an event_tlast_missing or event_tlast_unexpected error.

If you haven't, please review the product guides for both of these IP cores:

• https://www.xilinx.com/support/documents/ip_documentation/xfft/v9_1/pg109-xfft.pdf
• https://docs.amd.com/v/u/en-US/pg141-dds-compiler

[amna]

On 4/17/2024 at 2:19 PM, artvvb said:

Apologies for the delay. I haven't been successful in reproducing your setup. Some additional settings that might help are 1. the constant values applied to the CONFIG interface of the XFFT IP - I assume the tlast port is tied to a constant one. 2. XFFT settings - both the Configuration and Implementation tabs include settings that affect what values are provided to the CONFIG interface.

I'd also be curious about why the XFFT S_AXIS_DATA interface's tlast port seems not to be connected - in simulation, not asserting tlast at the expected time causes the XFFT core to assert either an event_tlast_missing or event_tlast_unexpected error.

If you haven't, please review the product guides for both of these IP cores:

• https://www.xilinx.com/support/documents/ip_documentation/xfft/v9_1/pg109-xfft.pdf
• https://docs.amd.com/v/u/en-US/pg141-dds-compiler

Hi @artvvb . I followed your guidelines and did the following changes in the design. The response of FFT is improved but not accurate. At first i was getting peak after 2 cycles but now its after about 10 to 11 cycles. Maybe I'm missing out some basic things to do this task.

Kindly guide me about it.

Edited Monday at 04:00 AM by amna