QoL Script for Vivado Block Design and PS-PL Communication

[artvvb]

A common issue that new users tend to run into, particularly with Zynq devices, is how to control custom modules in FPGA fabric from software. There are various techniques for this, including implementing custom AXI IP, using AXI GPIO controllers (what this post relies on), or using EMIO to control your modules via common communication interfaces (GPIOs, UART, SPI, etc). The goal of this post is to present a method for implementing this kind of communication that is relatively quick to set up and use, and that fits into a “standard” block-design-based workflow.

Custom commands in Vivado can be used to run TCL scripts via a button press or hotkey. Attached is a script that when run, will take all selected ports on IP in your block design and create an AXI GPIO for each of them. These pieces together make it so that module ports can be wired up to a processor with only a couple of clicks.

Note: This is intended as a way of building out a project quickly and potentially makes inefficient use of FPGA resources. It also doesn’t account for clock domains. I'd be curious for any suggestions for improvements that could be made.

Setup:

1. Download this script:create_register_file_from_selection.tcl. As is normal with downloading arbitrary code that will be run on your system from the internet, be careful and read through it before running it.
2. In Vivado, open the Tools -> Custom Commands -> Customize Commands dialog.
3. Click the plus button at the top of the list field to create a new command.
4. Pick a name, shortcut, etc. Importantly, select “Source Tcl file” and fill the path to your downloaded copy of the script into the corresponding text field.

The script is now installed. To run it for the first time, create a block diagram with some ports that you want to control. Select these ports by clicking on each of them. Use your hotkey or new button, found in the toolbar at the top of the screen, to run the script. You should see a new hierarchy created with several AXI GPIOs included, one connecting to each of your ports.

Before: The start and high_count ports of a custom counter module are selected.

After: GPIOs have been created for each of these ports. They can be connected to the PS as normal via connection automation.

It should also be noted that control-Z will undo the actions performed by the entire script (as startgroup/endgroup commands are used).

These GPIOs can then be used as normal from software, either by directly accessing their DATA registers or by using the xgpio driver. The following snippet of code could be used to toggle the start bit seen in previous screenshots.

#include "xgpio_l.h"
#include "xparameters.h"

// ...

u32 *start_reg = (u32*) (XPAR_CONTROL_0_START_GPIO_0_BASEADDR + XGPIO_DATA_OFFSET);
*start_reg = 1;
*start_reg = 0;

I hope this helps someone out there be a little more productive in Vivado, and as mentioned previously, am interested in feedback/suggestions.

-Arthur