AXI DMA TREADY help

[70cake]

Let me briefly introduce my block design. The input to the entire system consists of 8 I2S-formatted MEMS microphones. Through a custom IP, the serial data is converted into parallel data (32 bits). Subsequently, the signals are sequentially routed into a FIFO via a multiplexer (MUX). Afterward, the data from the 8 channels is concatenated using a data width converter (256 bits). Using DMA, the data is then transferred to the processing system (PS). Finally, on the PS side, the signals are packaged and transmitted back to the PC through the TCP protocol for further processing.

However, after receiving signals normally for a while, the TREADY signal of S_AXIS_S2MM goes low. This results in the data not being transmitted according to the sampling rate (16 kHz) but instead being delayed by many clock cycles before transmitting a signal.

The waveform chart below shows the initial normal signal transmission. The three AXIS from top to bottom represent MUX to FIFO, FIFO to data width converter, and data width converter to DMA, respectively. The frequency of the ws_4 signal at the top is the sampling rate (16 kHz). During normal transmission, the TREADY signals of the three AXIS remain high.

The moment TREADY of S_AXIS_S2MM goes low:

After a while, the TREADY from the FIFO also goes low, and then it takes many cycles before transmitting a signal again.

The signal received on the PC side (from one of the microphones) is shown in the following figure. The input signal is a 432 Hz sine wave. The waveform is initially normal, but it deteriorates later on.

I also found that TREADY of S_AXIS_S2MM goes low at the moment that customize IP & MUX are enabled. It can works normally for 4 clock cycles. At this moment, S_AXI_Lite and M_AXI_S2MM haven't started to do anything yet.

Thanks,

Darren

[artvvb]

Hi Darren,

How are you interacting with the DMA controller? If using SimpleTransfers and either interrupts or polling to check when a transfer is complete and restart the DMA, there will be some downtime while the processor is accessing various peripherals. Interrupts should respond quicker than polling, but still involve some AXI lite accesses that take a bit of time. Two recommendations would be to check the FIFO size to see if it can be increased to cover the downtime, and to connect the DMA's AXI lite and AXI S2MM interfaces to the ILA to take a look at how and when the DMA is accessed and sending data to DDR.

I may be misunderstanding the timing diagrams, but it looks like you're sending 8 words per transfer? One other possibility is that you could make transfers longer by sending multiple packets per transfer, by only sending a tlast bit for some of them, and modifying C sources as appropriate. This would reduce the frequency at which transfers need to be reinitiated.

I'm also curious how you are setting up transfers in software - a full reset of the DMA between transfers would take quite a bit of time.

Thanks,

Arthur