Reset package pin

[Suprith]

Can I know the package pin name in ARTY z7-10 devolopment board? I am not able to find the exact pin name in either reference manual and Schematic.

[zygot]

You can find all AMD/Xilinx device package pinout names and assignments here: https://www.xilinx.com/support/package-pinout-files.html

I'm not sure what you mean by RESET with regards to package pin names for FPGA devices.

[artvvb]

Hi @Suprith

The reset button on the Arty Z7 is not directly connected to the FPGA PL. Reviewing the schematic, the reset button, connected to the PS_RST net, triggers the PS side of the chip to reset and drives a reset on the CK_RST net, which is connected to the shield header reset pin. CK_RST is also connected to PS MIO12, however, this would not allow the PS to read a reset button press, since the upstream PS_RST will be applied.

Reset signals within the FPGA can alternatively be driven by resets associated with the FCLKs.

Thanks,

Arthur