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How to change slope in DAC


MaciejR

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Hi,

I am writing my own program in Python. And I have a problem.  I don't see a suitable function in the documentation (maybe there is another one that gives the possibility to set an output as a start value that is not an offset). I am looking for a way to set the output signal of the DAC (generator function: e.g. sin, ramp, triangle) as the start value of the voltage. What would help is to change the slope of the signal (picture with waves) I can even do it manually to get from the X to the Y value of the output voltage.

Actually the output is a value (from the current one) that has been calculated for a given phase shift (in this case 90 degrees). In one case this is -5V (DAC 2) or 0 (DAC 1). The offset control is not good because the amplitude signal saturates.

I've tried to find the function (I think it's related to the carrier frequency - picture from the SDK datasheet), but there are only "info functions".

 

BR

Maciej

 

image843.png

2023-09-14 at 22-55-05.png

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Thank you very much for the suggestion. Unfortunately the proposed functions do not work as I would expect. I have seen in the AnalogOut_Pattern.py sample files the use of this function. Unfortunately the voltage rises sharply for the 90 degree phase setting. The effect is as in the previous picture.

From what I understand, I have no influence on this anyway. Because the basic data for the generated signal is set. And then signal is set on the output pin of the DAC (from "internal generaor" designed in FPGA). Using  the function: dwf.FDwfAnalogOutConfigure(hdwf, channel, c_bool(True)) it is just set and run. 

I don't know how this has been implemented in AD2, my guess is that a digital DDS is made in the FPGA. And the only possibility is to set the amplitude (not the offset) from which to start the generator. This is possible with the phase setting, but it is done at one time. Because of this, the voltage at the output increases dramatically.

How to get around this restriction? Is there a hack for this? I was thinking of starting the amplitude with phase 90 (or 0) and then using AM modulation from 0 to max voltage. And the best option would be to add FM modulation to reduce the frequency (extending the setup time) and then set the target output frequency once the target output voltage is set. However, this could be problematic.
Is there an easier way to get a longer signal setting time. As I said. I can do this manually.  

Edited by MaciejR
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After my last message, I have tried something with changing  the offset. Unfortunately I don't understand what it's happend. I show it in the picture below. I set the offest from 0 to 5V in DC mode at the beginning, then I set the generator, switch on and change (with a delay of 0.8s) the offset n 0V. This offest change  causes the generator to switch off. This behaviour is not understandable to me. I have included the code below for ease of reference. 

 

 def Set_continuous():
        oxy = c_double(5)
        resolution = 200
        hzAcq_A = 200
        hzAcq_B = 5
        dwf.FDwfAnalogOutNodeEnableSet(hdwf, oCH_A, AnalogOutNodeCarrier, c_bool(True))
        dwf.FDwfAnalogOutNodeFunctionSet(hdwf, oCH_A, AnalogOutNodeCarrier, funcDC)
        dwf.FDwfAnalogOutNodeOffsetSet(hdwf, oCH_A, AnalogOutNodeCarrier, c_double(0)) #change offest
        time.sleep(0.05)
        dwf.FDwfAnalogOutNodeOffsetSet(hdwf, oCH_A, AnalogOutNodeCarrier, c_double(1)) # from 0V
        time.sleep(0.05)
        dwf.FDwfAnalogOutNodeOffsetSet(hdwf, oCH_A, AnalogOutNodeCarrier, c_double(2))
        time.sleep(0.05)
        dwf.FDwfAnalogOutNodeOffsetSet(hdwf, oCH_A, AnalogOutNodeCarrier, c_double(3))
        time.sleep(0.05)
        dwf.FDwfAnalogOutNodeOffsetSet(hdwf, oCH_A, AnalogOutNodeCarrier, c_double(4))
        time.sleep(0.05)
        dwf.FDwfAnalogOutNodeOffsetSet(hdwf, oCH_A, AnalogOutNodeCarrier, c_double(5)) # to 5V
        time.sleep(0.05)
        dwf.FDwfAnalogOutIdleSet(hdwf, oCH_A, DwfAnalogOutIdleOffset) 
        
        dwf.FDwfAnalogOutNodeEnableSet(hdwf, oCH_A, AnalogOutNodeCarrier, c_bool(True))
        dwf.FDwfAnalogOutNodeAmplitudeSet(hdwf, oCH_A, AnalogOutNodeCarrier, c_double(2.0)) 
        dwf.FDwfAnalogOutIdleSet(hdwf, oCH_B, DwfAnalogOutIdleInitial) # DwfAnalogOutIdleOffset
        dwf.FDwfAnalogOutIdleSet(hdwf, oCH_A, c_int(1)) # DwfAnalogOutIdleOffset
        
        dwf.FDwfAnalogOutNodeEnableSet(hdwf, oCH_A, AnalogOutNodeCarrier, c_bool(True))
        dwf.FDwfAnalogOutNodeFunctionSet(hdwf, oCH_A, AnalogOutNodeCarrier, funcSine)
        dwf.FDwfAnalogOutNodeFrequencySet(hdwf, oCH_A, AnalogOutNodeCarrier, hzAcq_A)     # 200 Hz
        dwf.FDwfAnalogOutNodeAmplitudeSet(hdwf, oCH_A, AnalogOutNodeCarrier, c_double(5)) # 5V
        dwf.FDwfAnalogOutNodePhaseSet(hdwf, oCH_A, AnalogOutNodeCarrier, c_double(90))    # 90 degree
        
        dwf.FDwfAnalogOutNodeEnableSet(hdwf, oCH_B, AnalogOutNodeCarrier, c_bool(True))
        dwf.FDwfAnalogOutNodeFunctionSet(hdwf, oCH_B, AnalogOutNodeCarrier, funcTriangle)
        dwf.FDwfAnalogOutNodeFrequencySet(hdwf, oCH_B, AnalogOutNodeCarrier, hzAcq_B)     # 5 Hz
        dwf.FDwfAnalogOutNodeAmplitudeSet(hdwf,oCH_B, AnalogOutNodeCarrier, c_double(5))  # 5V
        dwf.FDwfAnalogOutNodePhaseSet(hdwf, oCH_B, AnalogOutNodeCarrier, c_double(90))    # 90 degree
        
        dwf.FDwfAnalogOutConfigure(hdwf, oCH_A, c_bool(True))								# start generator for out A c_int(0)
        dwf.FDwfAnalogOutConfigure(hdwf, oCH_B, c_bool(True))								# start generator for out B c_int(1)
        time.sleep(0.8)																		# wati 0.8 s
        dwf.FDwfAnalogOutNodeOffsetSet(Dwf.hdwf, oCH_A, AnalogOutNodeCarrier, c_double(0)) 	# change offest to 0V



 

image843v.png
 

There is another interesting feature. If I add another function to the end of the code:

Dwf.dw.FDwfAnalogOutConfigure(Dwf.hdwf, oCH_A, c_bool(True))

The result will be as shown below. The generator is running again with a glich. 
2023-09-17at21-49-17.jpg.d8f70f6c9e27ecc1989196743474d3c8.jpg

I don't know why, changing offest ( dwf.FDwfAnalogOutNodeOffsetSet(Dwf.hdwf, oCH_A, AnalogOutNodeCarrier, c_double(0)) ) is turnning off the internal generator 

Edited by MaciejR
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