Zmod ADC 1410-40 clock routing problem

[Todd-Kairos]

I'm trying to bring up a Zmod ADC 1410-40 on an Opal Kelly Brain-1 carrier. When Vivado tries to Run Implementation, it gives the following errors.

[Place 30-126] Unroutable Placement! A BUFIO can only drive loads in the same IO bank. The following BUFIO clock loads are placed too far from the BUFIO to be routable. 
	design_1_i/ZmodScopeController_0/U0/InstDataPath/InstDcoBufio (BUFIO.O) is provisionally placed by clockplacer on BUFIO_X1Y8
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/GenerateIDDR[0].InstIDDR (IDDR.C) is locked to ILOGIC_X1Y95
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/GenerateIDDR[10].InstIDDR (IDDR.C) is locked to ILOGIC_X1Y98
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/GenerateIDDR[11].InstIDDR (IDDR.C) is locked to ILOGIC_X1Y97
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/GenerateIDDR[12].InstIDDR (IDDR.C) is locked to ILOGIC_X1Y94
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/GenerateIDDR[13].InstIDDR (IDDR.C) is locked to ILOGIC_X1Y91
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/GenerateIDDR[1].InstIDDR (IDDR.C) is locked to ILOGIC_X1Y149
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/GenerateIDDR[2].InstIDDR (IDDR.C) is locked to ILOGIC_X1Y111
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/GenerateIDDR[3].InstIDDR (IDDR.C) is locked to ILOGIC_X1Y80
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/GenerateIDDR[4].InstIDDR (IDDR.C) is locked to ILOGIC_X1Y79
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/GenerateIDDR[5].InstIDDR (IDDR.C) is locked to ILOGIC_X1Y138
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/GenerateIDDR[6].InstIDDR (IDDR.C) is locked to ILOGIC_X1Y100
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/GenerateIDDR[7].InstIDDR (IDDR.C) is locked to ILOGIC_X1Y137
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/GenerateIDDR[8].InstIDDR (IDDR.C) is locked to ILOGIC_X1Y96
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/GenerateIDDR[9].InstIDDR (IDDR.C) is locked to ILOGIC_X1Y112

	The above error could possibly be related to other connected instances. Following is a list of 
	all the related clock rules and their respective instances.

	Clock Rule: rule_gclkio_mmcm_1load
	Status: PASS 
	Rule Description: An IOB driving a single MMCM must both be in the same clock region if CLOCK_DEDICATED_ROUTE=BACKBONE
	is NOT set
	 ZmodDcoClk_0_IBUF_inst (IBUF.O) is locked to IOB_X1Y74
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/MMCME2_ADV_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1

	Clock Rule: rule_mmcm_bufg
	Status: PASS 
	Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/MMCME2_ADV_inst (MMCME2_ADV.CLKOUT1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/InstDcoBufg (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

	Clock Rule: rule_mmcm_bufr_bufio
	Status: PASS 
	Rule Description: An MMCM driving a BUFR/BUFIO must both be in the same clock region
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/MMCME2_ADV_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/InstBufrFeedbackPLL (BUFR.I) is provisionally placed by clockplacer on BUFR_X1Y4

	Clock Rule: rule_mmcm_bufr_bufio
	Status: FAIL 
	Rule Description: An MMCM driving a BUFR/BUFIO must both be in the same clock region
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/MMCME2_ADV_inst (MMCME2_ADV.CLKOUT2) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/InstDcoBufio (BUFIO.I) is provisionally placed by clockplacer on BUFIO_X1Y8
	ERROR: The above is also an illegal clock rule
	Workaround: < set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets design_1_i/ZmodScopeController_0/U0/InstDataPath/DcoPLL_Clk2] >

	Clock Rule: rule_bufh_bufr_ramb
	Status: PASS 
	Rule Description: Reginal buffers in the same clock region must drive a total number of brams less
	than the capacity of the region
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/InstBufrFeedbackPLL (BUFR.O) is provisionally placed by clockplacer on BUFR_X1Y4

	Clock Rule: rule_bufr_mmcm
	Status: PASS 
	Rule Description: A BUFR driving an MMCM must be placed within the same clock region
	 design_1_i/ZmodScopeController_0/U0/InstDataPath/InstBufrFeedbackPLL (BUFR.O) is provisionally placed by clockplacer on BUFR_X1Y4
 and design_1_i/ZmodScopeController_0/U0/InstDataPath/MMCME2_ADV_inst (MMCME2_ADV.CLKFBIN) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1

I tried adding the suggested workaround to my constraint file, and then got this error (and 7 more like it):

[Place 30-512] Clock region assignment has failed. Clock buffer 'design_1_i/ZmodScopeController_0/U0/InstDataPath/InstDcoBufio' (BUFIO) is placed at site BUFIO_X1Y8 in CLOCKREGION_X1Y2. Its loads need to be placed in the area enclosed by clock regions CLOCKREGION_X1Y2 and CLOCKREGION_X1Y2. One of its loads 'design_1_i/ZmodScopeController_0/U0/InstDataPath/GenerateIDDR[13].InstIDDR' (IDDR) is placed in site ILOGIC_X1Y91 in CLOCKREGION_X1Y1 which is outside the permissible area.

The Zmod Scope Controller user guide says the following, but does not provide enough details for me to know what constraints to add.

Quote

The IP does not constrain the clocks it requires as inputs, except for the DCO clock, therefore clocks need to be constrained in the top-level design either manually or by relying on the auto-derived constraints, if using clock modifying blocks. It is the user’s responsibility to correctly configure the input clocks of this IP. 

I'm generating all the clocks in the design from a single clock wizard, driven by FCLK_CLK3 at 200 MHz, configured with source=global buffer.

I'm obviously not very knowledgable about clock routing issues yet, and would really appreciate some help with this.

Thanks!

Edited August 29, 2023 by Todd-Kairos
Corrected typo

[artvvb]

Hi @Todd-Kairos

Really sorry for the delay. I tried reproducing this using Opal Kelly's pinout for the Brain-1 and preset from their Hello World project on Github  and was unsuccessful. The attempt is attached, though I can't confirm whether it would work in hardware. There are some details that could be helpful in diagnosing what's going on, in particular, I'd be curious what other clocks are being used in the design, and if other clocking wizards / MMCMs / PLLs are instantiated. Is there a chance you could share an archived project?

Paraphrasing the quoted part of the IP manual: The Zynq core automatically generates FCLK constraints and the Clocking wizard automatically generates constraints for the downstream clocks based on its params. Additional constraints shouldn't be necessary.

Thanks,

Arthur

 

brain-scope.xpr.zip

[Todd-Kairos]

Hi Arthur,

Sorry it took me so long to respond. I had a lot of trouble getting a Digilent Scope Zmod ADC 1410-40 module to work on the Brain SYZYGY Port C, so I connected the Digilent Zmod AWG 1411 to Port C instead, and used Ports A & D for my 2 Scope modules. This worked much better and I'm able to get them to operate (generating sinewaves on the AWG measuring them on the Scopes). However, there are still some very concerning warnings that I would like to address since these could cause problems or unreliability. Synthesis seems OK, but Implementation Route Design reports look problematic: particularly DRC - Route Design and Methodology - Route Design.

Some specific items of concern:

I defined pblocks for the hierarchy related to the AWG and each Scope module. It seems that these don't quite fit when placed, but I'm not sure how it still seems to work and does not report a critical error in this case. Here are the warnings from the DRC - Route Design report:

UTLZ-3#1 Warning
Resource utilization  - PBlock:pblock_adc_hier_PortA
DSPs over-utilized in Pblock pblock_adc_hier_PortA (This design requires more DSPs cells than are available in Pblock 'pblock_adc_hier_PortA'. This design requires 10 of such cell types but no compatible site is available in Pblock 'pblock_adc_hier_PortA'. Please consider increasing the span of Pblock 'pblock_adc_hier_PortA' or removing cells from it.)
Related violations: <none>

UTLZ-3#2 Warning
Resource utilization  - PBlock:pblock_adc_hier_PortD
DSPs over-utilized in Pblock pblock_adc_hier_PortD (This design requires more DSPs cells than are available in Pblock 'pblock_adc_hier_PortD'. This design requires 10 of such cell types but no compatible site is available in Pblock 'pblock_adc_hier_PortD'. Please consider increasing the span of Pblock 'pblock_adc_hier_PortD' or removing cells from it.)
Related violations: <none>

UTLZ-3#3 Warning
Resource utilization  - PBlock:pblock_dac_hier_PortC
DSPs over-utilized in Pblock pblock_dac_hier_PortC (This design requires more DSPs cells than are available in Pblock 'pblock_dac_hier_PortC'. This design requires 2 of such cell types but no compatible site is available in Pblock 'pblock_dac_hier_PortC'. Please consider increasing the span of Pblock 'pblock_dac_hier_PortC' or removing cells from it.)
Related violations: <none>

Methodology - Route Design report excerpts:

Note that the clock constraints from the two instances of Zmod ADC appear to conflict with each other. How should this be handled to ensure that both take effect? Should I make 2 copies of this constraint with distinct clock names in one of my main project constraint files?

TIMING-17#1 Critical Warning
Non-clocked sequential cell  
The clock pin design_1_i/adc_hier_PortD/ZmodScopeController_D/U0/InstDataPath/GenerateIDDR[0].InstIDDR/C is not reached by a timing clock

DPIR-1#1 Warning
Asynchronous driver check  
DSP design_1_i/adc_hier_PortA/ZmodScopeController_A/U0/InstCh2ADC_Calibration/cCalibMult0 input pin design_1_i/adc_hier_PortA/ZmodScopeController_A/U0/InstCh2ADC_Calibration/cCalibMult0/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability.  It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.

TIMING-18#1 Warning
Missing input or output delay  
An output delay is missing on ZmodAdcClkIn_n_D relative to the rising and/or falling clock edge(s) of ZmodAdcClkIn.

XDCC-1#1 Warning
Scoped Clock constraint overwritten with the same name  
A new clock constraint create_clock overrides a previous scoped clock constraint with the same name. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors.
New: create_clock -period 40.000 -name ZmodDcoClk -waveform {0.000 20.000} [get_ports ZmodDcoClk_A] (Source: /home/todd/kairos/projects/laser/acquisition/syzygy/laser_daq/hdl/block_design/ip/design_1_ZmodScopeController_0_1/ConstrsZmodADC.xdc (Line: 6))
Previous: create_clock -period 40.000 -name ZmodDcoClk -waveform {0.000 20.000} [get_ports ZmodDcoClk_D] (Source: /home/todd/kairos/projects/laser/acquisition/syzygy/laser_daq/hdl/block_design/ip/design_1_ZmodScopeController_0_0/ConstrsZmodADC.xdc (Line: 6))
Related violations: <none>

XDCC-1#2 Warning
Scoped Clock constraint overwritten with the same name  
A new clock constraint create_generated_clock overrides a previous scoped clock constraint with the same name. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors.
New: create_generated_clock -name ZmodAdcClkIn -source [get_pins InstADC_ClkODDR/C] -divide_by 1 -add -master_clock [get_clocks -of [get_ports -scoped_to_current_instance -prop_thru_buffers ADC_InClk]] [get_ports ZmodAdcClkIn_p_A] (Source: /home/todd/kairos/projects/laser/acquisition/syzygy/laser_daq/hdl/block_design/ip/design_1_ZmodScopeController_0_1/ConstrsZmodADC.xdc (Line: 1))
Previous: create_generated_clock -name ZmodAdcClkIn -source [get_pins InstADC_ClkODDR/C] -divide_by 1 -add -master_clock [get_clocks -of [get_ports -scoped_to_current_instance -prop_thru_buffers ADC_InClk]] [get_ports ZmodAdcClkIn_p_D] (Source: /home/todd/kairos/projects/laser/acquisition/syzygy/laser_daq/hdl/block_design/ip/design_1_ZmodScopeController_0_0/ConstrsZmodADC.xdc (Line: 1))
Related violations: <none>

I have attached an archive of the complete project, plus the 2 report files referenced above. Thanks in advance for your help sorting out these issues!

Todd

laser_daq_digilent_forum_2023_09_29.zip design_1_wrapper_drc_routed.rpt design_1_wrapper_methodology_drc_routed.rpt