NetFPGA_1G_CML QDRII+ IOSTANDARD isn't supported by VIvado MIG

[zygot]

I wanted to see if the QDRII+ memory on the NetFPGA_1G_CML board is usable, despite the glaring schematic error for the CY7C2263 part.

I'm using Vivado 2020.2 as that's the most recent version that I have a device license for. It uses the latest MIG 4.2 IP.

In the schematic the QDRII+ connections are properly terminated for HSTL_I_18. The CY7C2263 part is powered by 1.8V. The associated IO banks have a Vccio of 1.8V. The problem is that MIG only supports the HSTL_I ( 1.5V ) IOSTANDARD. This makes it impossible get through bitgen or to use this part of the board

Digilent did the design and manufacturing of the board and supposedly ( according to a reply to a previous post ) confirms functionality of the board. I've been unable to get anything from Digilent that proves this, or allows me to use the QDRII+ memory.

If Digilent is unwilling to provide a workaround then it should warn potential customers that the board is not fully functional as described in the user manual and schematic.

Edited August 8, 2023 by zygot