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VHDL I2C tri state IOBUF


Gaston1980

Question

I tried to create a simple i2C bus in vhdl. I created a project in XPS and create a ipcore in which a intent to create a i2c bus. I define the sda pin as INOUT. Due to this the VHDL has the IOBUF sda_I, sda_T and sda_O ports like this:

port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    --USER ports added here
         scl : 	out  STD_LOGIC;
         sda_I : 	in std_logic;
			sda_O : 	out std_logic;
			sda_T : 	out std_logic;
			Led :		out  STD_LOGIC;

I created a signals and define the control the IOBUF:

sda_T <= '0' when hab_sda_reg = '1' else '1';
sda_input <= sda_I ;
sda_O <= sda_out_reg;

I know that sda_T is the control of the IOBUF, the sda_I the input to my IP and the sda_O the output of my IP.

Using scope I can check my data is transmitted to the slave, but when I tried to read I can only see the line is floating even when i set the hab_sda_reg = '0'.

according to this picture if I set the control line sda_T to 1 the IOBUF will be in high Z and I will be able to read the input of sda, but from scope I checked and is floating. Why?

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Screenshot_20230624_153806.thumb.png.5570377aec56d7e129b37865660dde31.png

Edited by Gaston1980
wrong value in text
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I'm not up on XPS, nor is anyone else on the support team here. When using Vivado, an IP core having _I, _O, and _T ports, with a single _IO port not reflected in the IP but still showing up at the top level would be normal. If there's a way of checking whether the implicit IOBUF is actually being instantiated in the design, then that would be the thing to do; in Vivado, you might open the synthesized design, find the IO pin in a graphical view of the FPGA, and check to see if all three pins are connected internally. The physical hardware and how you have connections established is also relevant - do you have pullups resistors? What are you scoping?

Thanks,

Arthur

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