Help with Zynq tutorial

[zoodle]

I need a little help understanding this tutorial: https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi

Just over a third of the way down the page the tutorial starts talking about the AXI GPIO IP.  This sentence has me lost:

Quote

As can be seen, the individual ports that make up the interface are named <interface>_tri_i, <interface>_tri_o, and <interface>_tri_t. When constrained to tristate buffers, the bus that is connected to FPGA ports is named <interface>_tri_io.

I do not understand where this naming is coming from ("As can be seen").  On the diagram the AXI GPIO ports are labelled gpio_io_i, gpio_io_o and gpio_io_t.  I cannot find any reference to ***_tri_io.  

Any pointers appreciated!

[artvvb]

Hi @zoodle

You are correct, that looks to be a mistake in the guide. If you continue through the guide to the point where an HDL wrapper is created and open the HDL wrapper, you will be able to see the top-level port names in the port list, these top-level ports are the names that the constraints must match. The port will appear as either gpio_tri_io, gpio_tri_i, or gpio_tri_o, depending on whether the GPIO IP is set to tristate, all input, or all output. The three ports you see on the IP end up getting automatically connected to a tristate buffer in the final design.

Thanks

Arthur