Cmod S7 FPGA/GPIO series resistor

[Dams0622]

Hello,

I want to lower the series resistors (240 Ohms) connecting the FPGA to board GPIOs to reduce switching speed limitation (as stated in the board reference manual) and be able to make a 40MHz SPI interface work.
Where can I get the BOM or could you please provide me with the resistor reference? I am not familiar with SMD sizes.
Thank you

Damien

[zygot]

You can likely get away with 0 ohm series resistors, or a wire shunt, on GPIO pins. Tacking a solder bridge across an 0402 SMD resistor should be fairly east to accomplish ( intentionally or not ). Given the small PCB area of the CMODs an 0201 resistor is more likely to be what you are looking at, but Digilent needs to conform this. 

It would be swell if Digilent would provide a BOM for their FPGA boards like some other FPGA board vendors do. For a CMOD, the biggest problem might be finding the correct part on the board.

Just be aware that removing the series resistor increases the likely-hood of an accident or bad judgement damaging your FPGA device.

You might want to just try using the board as is. Start with a slower SPI SCLK and if that works increase it to your desired frequency. That would be a no cost experiment. 40 MHz isn't super high but you probably want to create SCLK from the FPGA clocking resources and use a clock output buffer with an enable. Slow slew rate settings and low current source capabilities to start might be a good idea.

Have you every tried soldering an 0201 size part before? It's not easy even with expensive soldering equipment.

[Dams0622]

Thank you,

It turns out to be a 0402 SMD, I used a ruler and found 1mm; I used a 50~R, and I will try what you suggested if that is not enough.
No, I never tried soldering a SMD in general and I had someone with good eyes helping me on that :)

I already have a design that works at 30MHz; it didn't before replacing the resistors because the limitation is 25MHz.

Now I am dealing with another problem, but off topic. I synchronize the SPI_SCK (which is an input for the FPGA and is not free running) with a 200MHz "master clock" but it looks like I am short 1 clock cycle, mostly due to the FF synchronizers introduced delays. I do not want to use a higher master clock just for this SPI interface so I am trying an implementation where SPI_SCK is treated as a clock. I saw the cmod s7 has 2 GPIOs on clock capable pins of the FPGA.
Hopefully I will post some waveforms within the next days

[zygot]

5 hours ago, Dams0622 said:

am trying an implementation where SPI_SCK is treated as a clock. I saw the cmod s7 has 2 GPIOs on clock capable pins of the FPGA

Any pin can be an output of a Series 7 internal clock. Only clock capable pins can be used as an input to the Series 7  clocking infrastructure.

An advantage of using a logic derived signal as a clock for an interface like SPI is that you can control timing in your HDL design explicitly. As the interface clock period starts approaching internal routing delays and IO buffer delays this approach start becoming unmanageable. The advantage of using an internal clock derived from an MMCM or PLL is that you can ( must ) provide timing constraints to help control timing. Output slew rate and current drive settings are all part of the design.  For either approach it's a good idea to verify signal timing relationships at the receiver end with a suitable scope. It's easy to under-estimate how much delay can be incurred due to place and route; and IO pins for an existing board are fixed.

The transmission line bandwidth requirements for sending a signal from source to destination is dependent on the signal slew rate, not toggling frequency. Transmission line bandwidth is one concern; managing overshoot and undershoot conditions at the receiver end by controlling impedance variation is another concern.

I don't actually have an S7 CMOD, so I was looking at an A7 CMOD. Every year those SMD resistors seem to be getting smaller when I look at them...

Edited May 24, 2023 by zygot