I2S2 Demo not working

[tidEman]

Hello,

I'm starting my journey with FPGA, therefore I bought a CMOD S7 board with I2S2 PMOD extension. Sadly, when I tried to run demo provided on the Digilent's site I wasn't able to run synthesis due to "clk_wiz_0_synth_1" error. Initially I tried to run this on the latest release of Vivado, but there was quite a few errors caused by compatibility, so I decided to change my version to 2018.2 so it can match the demo's release.

WARNING: [Synth 8-3301] Unused top level parameter/generic RESET_POLARITY
WARNING: [Synth 8-3301] Unused top level parameter/generic NUMBER_OF_SWITCHES
TclStackFree: incorrect freePtr. Call out of sequence?
 

These are the only errors I see in the log. The first two are pretty self explanatory, but the 3rd one is very confusing.
No changes have been made to any of the files.

If there are some better resources, that can help me learn how to at least bypass audio through the FPGA, I would be very happy to learn about them.

[artvvb]

Hi @tidEman, welcome to the forum,

Looking into fixing the issues, apologies that you're experiencing them.

Assuming you're following the "In order to program the project onto an FPGA" steps to download the Cmod S7 release archive and using "generate bitstream" to get a bitstream out of the projects, did you redownload the project archive between trying to open it in the latest version and in 2018.2? Just opening a project in a newer version could maybe change the underlying files.

The verilog sources should still be usable in recent versions, and the only change that was originally made to the default settings of the clocking wizard IP in the original version was to set it's CONFIG.PRIM_IN_FREQ to the appropriate clock frequency depending on the board being used. You could potentially delete the existing clocking wizard from the project, add a new one from the IP Catalog (found under Project Manager on the left side of the app), and change this setting to suit the board:

The top level parameters are the other thing to check. They can be found in the project settings, seen below, and override the parameters at the top of the top verilog file.

Thanks,

Arthur