More on that pesky MIO second UART

[engrpetero]

As I mentioned in another thread, I've added a second PS UART to a design on MIO pins 14-15.  The platform project has been updated and I'm back in Vitis.  By screwing around with the Xparameters.h, Xprint.c and Xprint.h files, I was able to send strings from Zybo_Z7 to PC over both UARTs, that is the USB UART and the Uart on MIO pins 14-15. I did restore the 3 mentioned files to their original content.

I decided I was wasting some time and really needed to use the already defined methods in the xuartps.h/c files.  And to get started, I downloaded the example projects the bsp pointed to (particularly the simple xuartps_hello_world_example).  It seems to make sense.  So I changed the define to what seemed should obviously send over UART0 (the one connected to MIO 14-15).  No luck - data is always transmitted over the USB Uart.  I even ran in Debug mode from Vitis, saw the expected 'base address', but still my laptop always receives data over the USB Uart, regardless which line I've uncommented below.  Any idea as to what stupid thing I'm doing wrong?

Edited March 6, 2023 by engrpetero

[engrpetero]

ugh.  The cable for the MIO UART was bad.  Comm over both PS Uarts seems to be working now and I can continue debugging.

[zygot]

I remember having issues with PS UART assignments using older versions of Vivado and the SDK. When you create a BSP and add support libraries make sure that the hardware and BSP assignments agree. Otherwise things get confusing. As I recall, the defaults settings in the SDK were opposite that of the hardware. Using the SDK you can easily check this. I don't use Vitis much but assume that that is also the case with the newer tools.

[engrpetero]

Thanks for the comments, @zygot.  Just another frustrating thing.  I have checked the BSP and support libraries and I agree with your observation that the hardware and BSP UART identifiers look backwards.  But at this point, all I care is that they are different.  Also, I'm not sure how Vivado/Vitis 'assigns' the base addresses (0xE0000000 or 0XE0001000) for the UARTs - I didn't see anything in the Zynq IP block in Vivado so I'm just assuming the base addresses are correct.

I keep two serial ports open on my laptop test app and just print a message anytime data is received on either port.  In Vitis, I simply change the DeviceID and then confirm while debugging on the hardware the expected base address is used.  All messages sent for the hardware though, regardless of the peripheral base address always show on only one of the laptop serial ports.  I'll continue looking and perhaps post on the Xilinx forums.