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How to Reconfigure AXI IIC IP in xilinx Vivado for external IR temperature sensor

Saikot Das Joy


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Hi @artvvb, I have done some modification in the block design and in constraint file , Please find it with the attachment, The bitstream generation is succesfull, but I am not sure either pin mapping is correct or not, if I dont include any constraint file, yet bitstream generation succeds. So I am confused. Would you please tell me how can I be sure that pin mapping is correct? When bitstream generation failed, it showed which pin to map, according to this I wrote the constraint file. I am also not sure, should I write any constraint file regarding VCC,and GND ? or leaving it as it is Screenshot2023-03-07143101.thumb.png.0b1afa8c04d4cd392478df387575addf.pngwill be just finScreenshot2023-03-07142902.thumb.png.6e57cdd834f171491643e39293302cf1.pnge?

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If you don't include a location constraint, I think Vivado picks one that it thinks would work for timing. This is probably somewhat useful when working on a project for which no PCB or dev board exists yet, and you are just in the early planning stages, but the behavior can be confusing. Constraints limit where Vivado is allowed to place design elements - if you don't tell it it has to place a port in a particular location, it's allowed to place it anywhere.

To tell that the constraints are correct, you should check the board schematic and the master XDC file, and compare them to your physical hardware setup. You can also look in the implemented design to find the placement of individual ports, which tells you that Vivado didn't map the port to some other undesired pin. A screenshot is below, where pin U16 is mapped to an output buffer that is connected to an LED. Vivado doesn't know the LED exists except by what it learns from the constraints (or board files if they were used) and top module.

Constraints aren't needed for the power rail or ground, since they aren't FPGA signals. For non-Zynq boards like the Nexys, you can tell which signals require location constraints by seeing which signals are present in the master XDC file and are connected to FPGA banks in the schematics.




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