I have made some verilog files, combined with a clockwizard to generate some fpga timing outputs.
These timings are controlled with some inputs that is to be controlled with the microblaze IP.
I've made the verilog files work perfectly, I can control them using IO26-IO27 and output on IO28-IO30 so I know that works.
I've also made a microblaze project that reads just fine from IO28-IO30 and writes to IO26-IO27, so I SHOULD be good to go.
Only problem is, that if I combine these two, I can only load one as a topfile and thereby only load one of them!?
So how do I program both the microblaze AND the verilog file to be run in parallel onto the FPGA?
Question
Jarl Gjessing
I have made some verilog files, combined with a clockwizard to generate some fpga timing outputs.
These timings are controlled with some inputs that is to be controlled with the microblaze IP.
I've made the verilog files work perfectly, I can control them using IO26-IO27 and output on IO28-IO30 so I know that works.
I've also made a microblaze project that reads just fine from IO28-IO30 and writes to IO26-IO27, so I SHOULD be good to go.
Only problem is, that if I combine these two, I can only load one as a topfile and thereby only load one of them!?
So how do I program both the microblaze AND the verilog file to be run in parallel onto the FPGA?
Thanks in advance
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