Jarl Gjessing

Would the right way be to. I.e. export the IP to a custom IP and then load it in the microblaze? Or maybe the other way around, load the microblaze exported HDL in the top.v file? This one I have a really hard time understanding how I could do with the humongous inputs and outputs :-)

I have made some verilog files, combined with a clockwizard to generate some fpga timing outputs. These timings are controlled with some inputs that is to be controlled with the microblaze IP. I've made the verilog files work perfectly, I can control them using IO26-IO27 and output on IO28-IO30 so I know that works. I've also made a microblaze project that reads just fine from IO28-IO30 and writes to IO26-IO27, so I SHOULD be good to go. Only problem is, that if I combine these two, I can only load one as a topfile and thereby only load one of them!? So how do I program both the microblaze AND the verilog file to be run in parallel onto the FPGA? Thanks in advance

I have a ARTY A7 board but cannot upload bitstream to it. I selected digilent as Vendor, and Arty A7-100 (On top of the FPGA there is a Artix-7 100T CSg324 label) And loaded one of the demo files. It compiles fine and generate the bitstream, but says: [Labtools 27-3303] Incorrect bitstream assigned to device. Bitfile is incompatible for this device. Bitstream was generated for device xc7z010i and target device is xc7a100t. In fact I cannot find any devices with the ID xc7a100t under parts they are all xc7z