Changing SET_VADJ while VADJ_EN is HIGH (Nexys Video)

[Chuting]

Hi,

I am using a Nexys video with another adapter card, which requires 2.5V from FMC connector. Currently I follow what the reference manual(page 6) says and set the control signals one by one in the stated order to set the FMC bank voltage to 2.5V:

VADJ_EN(low)->SET_VADJ(2'b10)->VADJ_EN(high) giving ~200ms between each step using a counter. 

I put this VADJ setting part before my main module (reset is deasserted when VADJ setting is done) and the whole thing works fine. But I am wondering if this VADJ setting sequence is really necessary and if I can just assign SET_VADJ=2'b10 in the beginning while VADJ_EN is high.

My guess as a beginner is that feedback voltage of the DC-DC regulator (ADP2384) becomes higher/lower than what it should be when SET_VADJ is changed while regulator is ON. It enters protection mode (output off) then the recovery time is hard to tell and it is not clear when to start the main module.

Is this one of the reasons why VADJ needs to be set in this particular way? or are there other reasons?

Thanks!

 

 

 

[JColvin]

Hi @Chuting,

I spent a bit of time digging in the ADP2384 datasheet (https://www.analog.com/media/en/technical-documentation/data-sheets/adp2384.pdf) and my understanding (as a non-power design engineer) is that you are are not beholden to wait the entire 200 ms between changing the state of the VADJ voltage.

I would still recommend turning off (disabling) the regulator before changing the VADJ because of the change in current draw and feedback voltage. True, you could ensure in your design that nothing is actively drawing extra current/in the middle of a process when their FPGA banks experience the voltage change and likely never encounter problems, but it is one of those "better safe than sorry/longevity" situations.

In terms of how long you need to wait, based on the Soft Start section of the datasheet (page 13), there is a 10.6 millisecond waiting time; if the output voltage is already charged prior to turning on the IC, there is some built in protection.

If you are changing the value of the VADJ voltage at the beginning before the rest of the design starts up and the .xdc is correctly set up, as long as any attached FMC card doesn't hate the changing voltage (I imagine most cards do not directly support being hot swapped) I would imagine that you could change the value directly, though it's probably safer to start with the output disabled before changing the voltage.

Let me know if you have any questions.

Thanks,
JColvin

[zygot]

For the Nexys Video I use an up counter that relies on the count being 0 before the end of configuration. VADJ_EN is de-asserted before the end of configuration. After configuration the counter start counting. Often I use a derived clock from an MMCM or PLL as my global counter clock so nothing happens until the MMCM clock outputs are stable an the pll_lock signal is asserted. At a certain count value I set the VADJ pins. At a later count value I assert VADJ_EN and stop the counter from counting until the device is re-configured again. If you want to provide a signal to your HDL application that VADJ is stable, then you can keep counting afte VADJ_EN is asserted until this is guaranteed, and then stop the counter. Don't allow the counter to be reset. This is the best solution that I;ve come up with. You definitely don't want to use an external reset pin for this.

I've never been enamored with how the Nexys Video works. User selectable Vadj is great but there's no reason to do it once the board has been turned on. The Genesis 2 does this using switches which is better.

The problem isn't just one of hot-swapping mezzanine boards. IO bank Vccio has to be chosen in your Vivado constraints before you can even have a bitream file to configure your FPGA with. You can't just decide to change IO bank voltages after bitgen creates a configuration file.

This is also a point of conflict with the SYZYGY DNA scheme. The idea there is that you can connect any pod with minimum and maximum Vccio requirements to any SYZYGY port and the system will decide what the actual Vccio is going to be assigned to a port based on other pods. The issue is that at this point the system doesn't guarantee that the Vccio that actually powers a particular pod is consistent with the IOSTANDARD that the Vivado tool were constrained to use during synthesis, P&R and bitgen. It's a bit of a problem.....

Don't get me wrong, I like the basic idea of SYZYGY. Having usable, consistent, very functional IO connectors beat the heck out of the slap-dash nonsense that is PMOD. I do think that trying to fiddle with Vccio during hardware system power-up hasn't been thought out that well.... Better to just make the user decide all of this when creating a bitstream and deciding what voltage to make Vadj before powering his system. At the very least the user will be forced to think about it rather than assume that *something else* will take care of everything. Edited February 17, 2023 by zygot