Nexys Video Board RGB2DVI PixelClk failed in block design

[miezekatzen_dompteur]

Hello,

i run a block design with the rgb2dvi IP block on a nexys video board. The pixel clock is 146MHz and the output at the HDMI device is 912x1140@120Hz. The output feeds a DLP4500 prjector from TI. The prjector needs the resolution of 912x1140 pix. When I synthesis the project I always get a error message

[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets hdmi_i/clk_wiz_0/inst/clk_in1_hdmi_clk_wiz_0_1] >

    hdmi_i/clk_wiz_0/inst/clkin1_ibufg (IBUF.O) is locked to IOB_X1Y124
     hdmi_i/clk_wiz_0/inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y3

    The above error could possibly be related to other connected instances. Following is a list of
    all the related clock rules and their respective instances.

    Clock Rule: rule_mmcm_bufg
    Status: PASS
    Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
     hdmi_i/clk_wiz_0/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y3
     and hdmi_i/clk_wiz_0/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

 

I use MMCM in the clocking wizard because PLL doesn't work with 146.0 MHz

 

 

Something went wrong with the PixelClk, here is the timing report.

How can I solve this problem...??

The project is under https://github.com/Johann-Schmid/hdmiAxi/

Have a great day & Thx

Edited February 6, 2023 by miezekatzen_dompteur

[zygot]

It's always appropriate to refer to the Xilinx device documentation. In this case a thorough reading of UG472 7eries Clocking Resources should help.

There are limitations for combining clock input pin selections. clock buffers, and CMT placement. Vivado provides a possible constraint work-around that will demote an error to a warning but doesn't recommend using that approach. You can try adding this constraint and see what happens, if you don't want to pick a different clock-capable input pin and connect your own clock source to it. That would be the preferable approach. A different input clock frequency might provide more flexible and better quality global clocking options as well.

One nice thing about video applications is that you can adjust pixel count/clocking frequency by changing the number of non-displayable pixels.

MMCM and PLL input clocks can come from external clock pins or global buffers. This allows, potentially, for using multiple CMT resources to create a global clock frequency that can't be created by one MMCM or PLL. Usually, selecting the appropriate external clock source and clock-capable input pin is the better approach. Unfortunately, some FPGA boards, like the Nexys Video, don't provide many options for users to provide external clocks. For the Nexys Video, you need to use the FMC connector to add an external clock to your design. Ultimately, timing closure comes down to basic starting decisions, like external clock frequency, clock input pin, and output pin assignments. If you are creating a custom FPGA board for a particular application it's possible to make optimal choices in the beginning. If you are designing a general purpose FPGA board for a wide range of applications it limits your ability to make starting design choices. That doesn't mean the the Nexys Video couldn't be better. Digilent's FPGA boards, in general, don't offer sufficient user clocking options. A significant factor in this is a refusal to update IO connector designs ( the PMOD ) as FPGA technology has move forward.

All FPGA devices have clocking regions. Xilinx clock routing rules tend to be less restrictive then Altera devices. Altera FPGA development boards have more external clock inputs. Whether this is better or worse, easier or more complicated to deal with, depends on your application. Edited February 6, 2023 by zygot

[miezekatzen_dompteur]

thx...I think i have to read the UG472