FMC connector for Nexys Video card

[Cedric]

Hello everybody,

I want to see if anyone of you know the characteristic impedance of the FMC connector for Nexys Video card (100, 50 or both) and  and which pins?

And I also wanted to know, if there are dedicated pins for high speed (for video process "I must use MIPI CSI2")?

I didn't find anything in the documentation about this and I'm starting with Xilinx FPGAs.

Thank you in advance,

Cédric.

[zygot]

This reply is sure to generate criticism, but I'll start the conversation anyway.

Talking about the characteristic impedance of a connector that isn't attached to anything doesn't make any sense. For information about the connector properties you need to refer to material from the connector vendor.

What you want to ask about is how the signal traces on the PCB that connect the FPGA pins to the connector are laid out. Most of the signals for a Vita-57 style interface are designed to support differential signalling. That doesn't mean that all boards using FMC LPC or HPC type connectors are used this way. There are different way to arrange signal traces on a PCB for differential signalling. One uses spacing between the signal pairs on one layer referenced to ground plane on another layer. You can also put the pair traces on different layers. When you don't want to constrain connector functionality to differential signalling, you can just length match signal pairs and pace the traces far enough apart from each other to minimize coupling, making the connector adequate for single-ended signalling applications or differential signalling applications. This is used with the HSMC type connector alll the time and varies from board to board for both carrier and mezzanine card. Same with FMC. Differential signalling has impedance properties with respect to the _n and _p pair to each other and the _n and _p pins with respect to a ground reference. How one implements PCB trace routing depends on what "high speed" means for your application. It's not necessarily as simple as talking about toggling rates for individual signals. Anyone can find equations for determining PCB trace impedance for a given layout strategy on the web. You will need to know what type of material the PCB is made of. If you are doing something that requires particularly high performance then you want to reduce or eliminate things, like vias, that create impedance disruptions along the signal trace. No vias are ideal but not usually possible with high performance connectors.

Series 7 devices do not support Mipi compatible IO logic standards, though it's possible to emulate receivers it as some of Digilent's products do. For a high quality interface you are probably better off using a Mipi PHY device on your FMC mezzanine card to translate signalling characteristics between source and terminus devices. Digilent does publish pcb trace length information which you will need.

Series 7 devices support limited programmable receiver delay for IO when pins or pairs of pins are bussed. For signals driven by the FPGA, you need to account for length mismatch issues on the mezzanine card.

Edited February 2, 2023 by zygot

[Ionut]

Hi Cedric,

The FMC connector on Nexys Video (J1) has 34 differential signal pairs (in the schematic, FMC_LAxx_P and FMC_LAxx_N respectively, with xx going from 00 to 33), connected to the FPGA. These signals are routed with 100 ohms differential impedance for each pair (i.e. _P and _N). The corresponding FPGA pins are powered from the VADJ adjustable supply rail (1.2V...3.3V).

Also, there is a Gigabit transceiver lane wired to the FMC connector (FMC_MGT_C2M_P and FMC_MGT_C2M_N going out from the FPGA, and FMC_MGT_M2C_P and FMC_MGT_M2C_N going into the FPGA) and its accompanying clock lane (FMC_MGT_CLK_P and FMC_MGT_CLK_N going into the FPGA). These signals are also routed with 100 ohms differential impedance for each pair.

Regarding MIPI CSI2, Xilinx Series 7 FPGAs do not natively support the D-PHY interface for CSI2 interfaces. However, there are compatible solutions (described in this Xilinx application note: https://docs.xilinx.com/v/u/en-US/xapp894-d-phy-solutions). We have implemented such a compatible solution on Zybo Z7, for a camera interface (Pcam 5C).

Other MIPI implementations on Digilent products can be found on FMC Pcam Adapter (which has 4 unidirectional MIPI ports for cameras like Pcam 5C, implemented using MC20901 level translators) and on Genesys ZU (which has two bidirectional MIPI ports, natively supported by Zynq Ultrascale+).

I hope this helps.

Please let me know if you have any other questions.

Best Regards!

[thinkthinkthink]

Hi!

We also have a demo project for the Genesys 2 using the FMC-Pcam-Adapter together with 4 Pcams. Here's the link to the Vivado 2022.1 hardware branch and the Vitis 2022.1 embedded software branch.

This example project should work with the Nexys Video too however there are certain changes that need to be made. Firstly, the MIG settings need to be changed to match those in the Nexys Video's Reference Manual and the board constraints also need to be carefully adapted from one board to another one reason being that the Genesys 2 has a kintex7 fpga while your board has an artix7.