Pmod AD1

[Udayan Mallik]

@artvvb I am using two AD1 cards to ingest 4 channels of ADC data. As per @JColvin's directions, I instantiated the Pmod_AD1 data handler in my FPGA and connected all 8 ports of that module to 8 corresponding pins in the FPGA.

Does this imply that the Pmod AD1 module is designed to interact with 2 AD1 cards at all times?

Udayan Mallik

Edited December 13, 2022 by Udayan Mallik

[artvvb]

Yes, as long as you are using make external, you need to use two AD1 modules to control two Pmod AD1s, and you are able to constrain the each module's ports to the pins of a single Pmod port. The Pmod pins you use for each port in this case are arbitrary - you can map whatever module port to whatever physical location using the XDC - so top row and bottom row is doable.

Thanks,

Arthur

[artvvb]

Hey Udayan,

No, a single Pmod AD1 controller only controls a single Pmod AD1. Assuming you use the board file interface, it must be connected to the top row of the Pmod port the module is attached to - due to limitations of the Pmod IP when its used in this way, the lower four pins must be constrained, but are not attached to any logic in the FPGA.

Thanks,

Arthur

[Udayan Mallik]

@artvvb Thank you for your response.

First - I cannot use the board file interface to connect the module to its pins. I do so using the Make External instruction.

Second, I use two AD1 cards. Can I instantiate two AD1 modules in the FPGA and connect the IO of the second to the lower row of the PMOD port?

Udayan Mallik

Edited December 15, 2022 by Udayan Mallik

[Udayan Mallik]

@artvvb I now have a different problem. "Generate Bitstream" does not generate a bit file. I get the attached message - since I do not assign 4 of the pins to any location "An unspecified IO Standard Error" is generated. How do I get around it? Assign random pins to these ports? Do you have a list of pins that cannot harm the operation of the card.

[artvvb]

Assigning random pins should work. I'd suggest using pins from another Pmod port, if you have any that are unused/free.

[Udayan Mallik]

@artvvb I have other use for the other PMOD port. Any reason I cannot use one of the unconnected pins in Bank 35 (3.3V)? For example B19, C19 and the other pins in that neighbourhood. 

[artvvb]

I would assume it's fine to use other unconnected pins, but I'm not sure. The AD1 IP doesn't connect any signals to the pins, it just needs to know that they are there. I'd mostly be concerned about something like shorting an output logic high to ground, but that shouldn't happen here with no actual output signal, and no path to ground from the pin.

[Udayan Mallik]

@artvvb Assigning to unconnected pins has solved my problem.

Edited December 20, 2022 by Udayan Mallik

[Udayan Mallik]

@artvvb Does Pin 1 of the Pmod_AD1 module (instantiated in the FPGA) correspond to Pin1 of the JA and JB ports in Eclypse Z7.

[artvvb]

It depends on your XDC file. Pin 1 of the IP/module is intended to be connected to Pin 1 of the physical pmod port (same goes for the rest of the pins, 2-4, 7-10). However, the XDC file decides what pin on the IP actually connects to what physical FPGA pin. This means you can constrain one module's pins 1-4 to pins 1-4 of JA, constrain another module's pins 1-4 to pins 7-10 of JA, and pins 7-10 of both modules to whatever other FPGA I/O is available.

[Udayan Mallik]

@artvvb The Make External command creates ports inside the FPGA that are all outputs. The two Data bits are inputs. How is that part of the problem handled.

[artvvb]

The ports you are referring to are likely interface ports, which are effectively buses made up of multiple individual ports/signals. Check your HDL wrapper file to determine the actual ports which are created for your design - I expect you will find sixteen inouts instead of two output ports, see below for an example with one interface port.

Thanks,

Arthur

Quote

  inout Pmod_out_0_pin10_io;
  inout Pmod_out_0_pin1_io;
  inout Pmod_out_0_pin2_io;
  inout Pmod_out_0_pin3_io;
  inout Pmod_out_0_pin4_io;
  inout Pmod_out_0_pin7_io;
  inout Pmod_out_0_pin8_io;
  inout Pmod_out_0_pin9_io;