SD data I/O configuration for Genesys ZU boards

[John J]

In both the 3EG and 5EV board presets, drive pullup and speed for data bit 4 of the SD card are configured differently than the other 7 bits.  Is this correct?

I realize that all bits may not be treated identically on the interface, but thought I'd ask.

 

preset.xml:             <user_parameter name="CONFIG.PSU_MIO_39_PULLUPDOWN" value="disable"/>
preset.xml:             <user_parameter name="CONFIG.PSU_MIO_39_DRIVE_STRENGTH" value="4"/>
preset.xml:             <user_parameter name="CONFIG.PSU_MIO_39_POLARITY" value="Default"/>
preset.xml:             <user_parameter name="CONFIG.PSU_MIO_39_INPUT_TYPE" value="cmos"/>
preset.xml:             <user_parameter name="CONFIG.PSU_MIO_39_SLEW" value="slow"/>
preset.xml:             <user_parameter name="CONFIG.PSU_MIO_39_DIRECTION" value="inout"/>

preset.xml:             <user_parameter name="CONFIG.PSU_MIO_40_PULLUPDOWN" value="pullup"/>
preset.xml:             <user_parameter name="CONFIG.PSU_MIO_40_DRIVE_STRENGTH" value="12"/>
preset.xml:             <user_parameter name="CONFIG.PSU_MIO_40_POLARITY" value="Default"/>
preset.xml:             <user_parameter name="CONFIG.PSU_MIO_40_INPUT_TYPE" value="cmos"/>
preset.xml:             <user_parameter name="CONFIG.PSU_MIO_40_SLEW" value="fast"/>
preset.xml:             <user_parameter name="CONFIG.PSU_MIO_40_DIRECTION" value="inout"/>
 

 

Edited November 29, 2022 by John J

[elodg]

From pg201:

Port sdio_data_out[4] is SDIO_SEL in our schematic. It is a control signal for the level translator instead of SDIO interface proper. We determine drive levels using board-level simulation and prototype validation.

Edited December 5, 2022 by elodg

[JColvin]

Hi @John J,

I have reached out to get some more insight into this question.

Thanks,
JColvin