pmod ssd and zc706 board

[mahinay]

HI i'm using zc706 board and I'm trying to use a pmod ssd in the zc706 board as a practice....My question is how to make or find a board or master board library for inserting pmod ip all I can find is library of zybo board or arty 

[artvvb]

Hi @mahinay,

Welcome to the forums.

Digilent doesn't provide a Pmod IP core for the Pmod SSD. That said, there should be examples out there which will fit your needs. What are you trying to practice? The route you take will differ pretty strongly depending on whether you want to get data from the Zynq processor on the ZC702 onto the display, or if you are trying to get data from elsewhere in the Zynq PL onto the display.

Thanks,

Arthur

 

 

[mahinay]

Hi thanks for the reply, I actually tried to use a pmod ssd to my zc706 board and after inserting the pmod gpio in my block design ,I was about to re-customize IP  but the Ip interface and board interface does'nt show up . I was thinking maybe it need a IP library for my board but I can't find any

[artvvb]

Sounds like the ZC706 board files might not have Pmod interfaces defined. In this situation, you can create external ports and write constraints for the Pmod pins manually. Check out the second half of the "Adding GPIO Peripherals to a Block Design" section of this guide on Reference: https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi#add_gpio_peripherals_to_a_block_design.

Since the Pmod GPIO IP uses a different interface from the AXI GPIO, the top-level port names that need to be written into the XDC file may differ. You can check for the names you need to constrain by opening the HDL wrapper file after you've validated your block design and created the wrapper. - You should see some pins like "Pmod_out_0_pin1_io". See below for an example:

Note that you can also use the same method with an AXI GPIO IP.

Thanks,

Arthur

[artvvb]

If bit-banging a seven segment "protocol" through GPIO isn't working well, you might consider writing a custom seven segment controller, adding it to a block design through "Add Module", and connecting it to an AXI GPIO to provide a simple interface from the processor. The custom logic might only need to include a counter that drives the C pin and a mux to select 7 from a set of 14 bits that the processor can write to.

Using this stub verilog module:

Quote

module test(
    input clk,
    input [13:0] c_data,
    output [7:0] pmod_pins
    );
endmodule

It can be wired to an AXI GPIO and external ports like this:

Thanks,

Arthur

[Tim S.]

Over two years ago, I authored a driver for the Pmod SSD that uses minimal CPU overhead. You can find it in the Project Vault. I titled it MuxSSD. Regards, Tim S.

 

[mahinay]

Thank you very much for your time  and now I am working on the project using your advice!