Using MB with DDR2 cannot reset correctly

[KBlueLeaf]

I have a Nexys A7-100T, I have tried to use MB without DDR2 on it and just work perfectly.
When I push the reset button, it can just run the program again.

But this time I try to use MB with DDR2, I use SREC SPI Bootloader to load my program in to dram.
I can work, when I push the program button it could just load whole thing and run correctly.
But this time when I push the reset button, It just reprint something but not reload the bootloader again.
Example:

1st run:
SREC SPI Bootloader
FlashID=0x1 0x20 0x18
Loading SREC image from flash @ address: 003d0900
Bootloader: Processed (0x)00001007 S-records
Executing program starting at address: 00000000
Hello World
Successfully ran Hello World application

After push reset button:
?ran Hello Worl

the reset signal is like below:
reset btn -> MIG's sys_rst(Activate Low)
MIG's ui_clk_syn_rst -> rst_mig_7series_0_81M & rst_clk_wiz_0_200M & clk_wiz
↑All of them are Activate High
rst_mig_7series_0_81M's mb_reset -> Microblaze(Activate High)
rst_mig_7series_0_81M's peripheral_aresetn -> axi_smc & mig's aresetn
rst_clk_wiz_0_200M's peripheral_aresetn -> axi_uarlite & axi_quad_spi's s_axi_aresetn

The whole graph is like this

 

Did I just do something wrong?
Or the reset signal is just not work for design with ddr2?

[elodg]

In MIG designs where the processor and system clock is dictated by the DDR frequency and its clock ratio, the MIG should be the first to reset which stops the clocks, issues resets down the line, re-establishes clocks and releases resets. Do NOT use the processor system reset block to reset MIG. Either tie the external reset to MIG, or not reset the MIG at all, just the rest of the system.

[KBlueLeaf]

56 minutes ago, elodg said:

In MIG designs where the processor and system clock is dictated by the DDR frequency and its clock ratio, the MIG should be the first to reset which stops the clocks, issues resets down the line, re-establishes clocks and releases resets. Do NOT use the processor system reset block to reset MIG. Either tie the external reset to MIG, or not reset the MIG at all, just the rest of the system.

the reset for MIG is from reset button, other part's reset signal is from MIG.
And I'm using Nexys A7 which FPGA core is Artix7 (which doesn't have Processor System) so I don't know what you mean about the PS's reset block.

My MIG's reset is from external.
Other part's reset is from MIG's ui_clk_sync_rst and clocking wizard's clk src is MIG.
I think what I have is what you say, And that's why I am wondering how could this happen.

[KBlueLeaf]

Oh, I mistook what you said and I find the "reset" from "PS reset".
I'll try what you say.
And "thanks" to the auto connection

[KBlueLeaf]

Wait, I search for this and find that everyone connect the aresetn to Processor System Reset.
And it looks like this reset signal is for reset AXI but not MIG itself and what I have now seem should be correct