To make a long story short (you can find the whole tale here on the xilinx forums if you're curious - still ongoing), I'm trying to use your zyboz7tutorials to set up a unit test of the Xilinx MIPI-CSI-2 Rx Subsystem on the Zybo Z7020 w/ pcam 5c. In it's simplest form, I'm trying to build the camera input chain from your petalinux 2017.4 demo in 2021.2 (both vivado and petalinux) using the 5.1 version of the IP and 5.0 version of the driver (supposedly compatible). I've tried variants based on Xilinx' documentation, and based on both of your tutorial designs (and every combination of the three that made sense). Regardless of what configuration (DT/Petalinux/HW Design) I use, I experience a kernel panic upon driver probe/access of the MIPI-CSI-2 IP's registers. Possibly when I access any register on any IP, but I can't verify that. The Framebuffer IP also in use doesn't access a register during device probe (that I can see), and the panic prohibits further analysis so far.
As mentioned in the longer thread over in Xilinx land, the extensive searching and debugging I've engaged in so far has left me with at least some reason to believe this is a configuration issue (I've been pointed towards resets, though that hasn't yielded results yet), but no efficient way to narrow down what it might be.
The other thought that occurred to me is that it might be an artifact of upgrading the IP in vivado, since that's the only other thing that changed in one case (I tried importing the working 2017.4 hw design, and stripped it down to a close approximation of my unit test only to find the same kernel panic). I guess upgrading IP isn't as straightforward as I'd like. Which leads me to the reason for this question:
In the course of maintaining and updating the petalinux demo project for this board, have your engineers ever run into this or any similar issue (kernel panic upon accessing IP registers via axi-lite)? If so, are you able to point me towards the root cause of the problem?
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westam
Apologies for the unclear title.
To make a long story short (you can find the whole tale here on the xilinx forums if you're curious - still ongoing), I'm trying to use your zyboz7 tutorials to set up a unit test of the Xilinx MIPI-CSI-2 Rx Subsystem on the Zybo Z7020 w/ pcam 5c. In it's simplest form, I'm trying to build the camera input chain from your petalinux 2017.4 demo in 2021.2 (both vivado and petalinux) using the 5.1 version of the IP and 5.0 version of the driver (supposedly compatible). I've tried variants based on Xilinx' documentation, and based on both of your tutorial designs (and every combination of the three that made sense). Regardless of what configuration (DT/Petalinux/HW Design) I use, I experience a kernel panic upon driver probe/access of the MIPI-CSI-2 IP's registers. Possibly when I access any register on any IP, but I can't verify that. The Framebuffer IP also in use doesn't access a register during device probe (that I can see), and the panic prohibits further analysis so far.
As mentioned in the longer thread over in Xilinx land, the extensive searching and debugging I've engaged in so far has left me with at least some reason to believe this is a configuration issue (I've been pointed towards resets, though that hasn't yielded results yet), but no efficient way to narrow down what it might be.
The other thought that occurred to me is that it might be an artifact of upgrading the IP in vivado, since that's the only other thing that changed in one case (I tried importing the working 2017.4 hw design, and stripped it down to a close approximation of my unit test only to find the same kernel panic). I guess upgrading IP isn't as straightforward as I'd like. Which leads me to the reason for this question:
In the course of maintaining and updating the petalinux demo project for this board, have your engineers ever run into this or any similar issue (kernel panic upon accessing IP registers via axi-lite)? If so, are you able to point me towards the root cause of the problem?
Thank you for your time
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