Problem with FMC PCAM adapter board, only one MIPI line used, on ZCU102 board

[gba]

We want to connect a single PCAM 5C board https://digilent.com/reference/add-ons/pcam-5c/start to the Xilinx ZCU102 board, FMC port HPC0 of the board.

For the MIPI IP, I adapted the code available for the ZYBO board which works perfectly for the 7 series architectures, (several projects on ZYNQ7 with different architectures work well) and adapted the primitives to the Ultrascale architecture in particular.
On the ZCU102 board, the SCCB (IIC) line works correctly and I can set the sensor registers. The sensor config used is this one : cfg_1080p_30fps_336M_mipi_

I have a problem with the MIPI_DPHY. The acquisition of the clock line is done correctly, (SCNN), the mmcm block locks correctly on it. On the other hand, on the data lines (SFEN), and their de-serialization with the ISERDESE3 primitive (which follows an IDELAYE3), I always have X "00" or X "FF" in output of the SERDES. So my component never locks to the kSyncSeq which should be from the sensor at the beginning of the MIPI sequence

This is how my MIPI entries are constrained:

set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS18} [get_ports dphy_clk_lp_n]

set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18} [get_ports dphy_clk_lp_p]

set_property IOSTANDARD LVDS [get_ports dphy_hs_clock_clk_n]

set_property DIFF_TERM_ADV TERM_100 [get_ports dphy_hs_clock_clk_n]

set_property PACKAGE_PIN AB4 [get_ports dphy_hs_clock_clk_p]

set_property PACKAGE_PIN AC4 [get_ports dphy_hs_clock_clk_n]

set_property IOSTANDARD LVDS [get_ports dphy_hs_clock_clk_p]

set_property DIFF_TERM_ADV TERM_100 [get_ports dphy_hs_clock_clk_p]

set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18} [get_ports {dphy_data_lp_n[0]}]

set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18} [get_ports {dphy_data_lp_p[0]}]

set_property IOSTANDARD LVDS [get_ports {dphy_data_hs_n[0]}]

set_property IOSTANDARD LVDS [get_ports {dphy_data_hs_p[0]}]

set_property PACKAGE_PIN W5 [get_ports {dphy_data_hs_p[0]}]

set_property PACKAGE_PIN W4 [get_ports {dphy_data_hs_n[0]}]

set_property DIFF_TERM_ADV TERM_100 [get_ports {dphy_data_hs_n[0]}]

set_property DIFF_TERM_ADV TERM_100 [get_ports {dphy_data_hs_p[0]}]

set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18} [get_ports {dphy_data_lp_n[1]}]

set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18} [get_ports {dphy_data_lp_p[1]}]

set_property IOSTANDARD LVDS [get_ports {dphy_data_hs_n[1]}]

set_property IOSTANDARD LVDS [get_ports {dphy_data_hs_p[1]}]

set_property PACKAGE_PIN AC2 [get_ports {dphy_data_hs_p[1]}]

set_property PACKAGE_PIN AC1 [get_ports {dphy_data_hs_n[1]}]

set_property DIFF_TERM_ADV TERM_100 [get_ports {dphy_data_hs_n[1]}]

set_property DIFF_TERM_ADV TERM_100 [get_ports {dphy_data_hs_p[1]}]

set_property IBUF_LOW_PWR FALSE [get_ports {dphy_data_hs_p[0]}]

set_property IBUF_LOW_PWR FALSE [get_ports {dphy_data_hs_p[1]}]

set_property IBUF_LOW_PWR FALSE [get_ports dphy_hs_clock_clk_p]

My voltage reference from bank 66 of the ZCU102 is 1.8V.

When I inspect the MIPI signals on the scope, I do have a VCM at 1.2V and a VDO-diff that looks correct.

On this post

https://forum.digilent.com/topic/22878-connect-2-or-more-cameras-to-genesys-zu-board/#comment-66895

it is said in the first place that the FMC PCAM card is not compatible with the ULTRASCALE architecture, if the 4 MIPI inputs are used.

It says here:

https://digilent.com/reference/add-ons/fmc-pcam-adapter/reference-manual?redirect=1#fpga_io_architecture_compatibility that 1 or 2 MIPI lines may well be used.

Does anyone have any idea what is wrong or has anyone already adapted the code developed for the 7 series architecture to the Ultrascale MIPI architecture to tell me what pitfalls to avoid?

[gba]

Nobody to answer my question? 

To be less specific in my request, has anyone ever run the FMC PCAM board, with a single MIPI camera head connected, on a board with a Soc or FPGA with an Ultrascale architecture like the ZCU102, ZCU104 or ZCU106 boards?