Vivado setup must be incorrect

[craigFirst]

I have downloaded and am using Vivado 2022.1 on a new AMD 5950 computer.  All loaded, everything works and I can communicate and program the board.  Quick test shown below lights the led with the switch (it works just fine).  However, I must be setting something up with Vivado itself incorrectly.  For example, to only synthesize the following:

module top_module (input switch, output led);

     assign led = switch;

endmodule

Takes almost 1 minute, and to implement is longer.  This cannot be correct.  I am worried about when I start to write actual, longer verilog it will become too slow to get any work done.  (Quartus on the same computer takes only moments.)  Before I panic, is Vivado really this slow?

[zygot]

What's your OS?

The last version that I installed was VIvado 2021.2. I only use it for UltraScale ZYNQ projects. I have 3 other versions of Vivado installed on a WIN10 box

After installing Vivado 2021.2 I noticed that it takes a very long time to start up. Sometimes I get a timeout message after 3 minutes of waiting.. and then it might start, or not, anyway. What's weird is that now all of my versions of Vivado take a long time to start up. My Win10 box is never connected to the internet except for OS and software updates.

So, with that in mind, have you tried running Vivado without an active internet connection?

There's another possibility. Your attempt at a compiling what you consider a trivial test module might be problematic for the tools. Perhaps you discovered a version bug. Try adding a clock input and setting your LED using a clocked process.

For most of my work I use VIvado 2019.1 because I know its bugs. I would suggest that a tool version that dates to around when your board was first introduced, or what any board vendor demos were built on is a good way to go. as any Win** user knows, newer isn't necessarily better. Heck, Vivado 2015.3 is just fine, and possibly better, for any run of the mill Artix based board. I still use it on a linux host occasionally.

The short answer is that no, it shouldn't take a minute to synthesize your code as it currently exists. It might be that there are synthesis messages that might indicate some unexplained problem. Vivado does some funky, and sometimes very disturbing, things in an effort to "speed" up the user experience. It has a too complex database system and sometimes can't keep track of storage in memory and storage on disk. Even the 2020.2 edition is capable of running synthesis and implementation for very large and complex designs with many clock domains in a reasonable amount of time. The definition of the word reasonable of course being related only to personal expectation which is kind of meaningless. Edited September 13, 2022 by zygot

[craigFirst]

OS is a fresh install of Windows 10.  Computer is new: AMD 5950 running near 5Ghz, all SSD, 32Gb of memory.

The FPGA board is NEXYS A7-100t (brand new) from digilent.

I made sure to have the board files loaded and selected in the project, and the constraint file also.  No other changes.

Do you know which version of Vivado should I be using for this FPGA?  I'll download that tonight.

[JColvin]

Hi @craigFirst,

The FPGA on the Nexys A7-100T is compatible with any version of Vivado. I recently had some super slow connection issues with Vitis 2021.2 reminiscent of what is mentioned in this Xilinx thread (https://support.xilinx.com/s/question/0D52E00006rV1B5SAK/20212-hwserver-working-very-slow?language=en_US) though updating my install to 2021.2.1 did not resolve the issue for me.

Anecdotally, I've heard that 2022.1 runs more smoothly (I can't verify if it does or not, apparently it is not for you, though I), so realistically I would probably download an older version of Vivado, if only for the smaller overall file size. If it matters to you, the demos Digilent has for the Nexys A7 (https://digilent.com/reference/programmable-logic/nexys-a7/start#example_projects) have releases for 2018.2, 20.1, 21.1, and 22.1.

I did run a comparison of this example for the Nexys A7 100T in different versions of Vivado (with Verilog as the target language) with times as reported by Vivado in the Design Runs tab.

2018.2: synth -- 22 seconds; impl -- 59 seconds

2020.1: synth -- 25 seconds; impl -- 54 seconds

2022.1: synth -- 32 seconds; impl -- 1 min 02 seconds

If you go off of that data alone, it seems that maybe 2020.1 might be a good option, but based on what you described, none of these will necessarily classify as "moments" like you described with Quartus. Your mileage may very of course, though like @zygot indicated, you might want to go for an older installation. Xilinx isn't a fan of backwards compatibility though, so be aware of that if you're using any sort of existing block designs.

I know there are some options for increasing the number of threads for different portions of the synthesis and implementation, though a surprising number of them are limited to 2 cores no matter what you might have selected in the pop-up (though perhaps I doing it wrong).

If I'm being honest, I just limit the maximum amount of cores the Xilinx software has access to on my computer, and then just find other things to do in the meantime.

Thanks,
JColvin

[zygot]

I tried to post an answer yesterday, but the site was down every time I had a chance to do it.

Jon pretty much posted everything that I was going to say, but with a few more details. The latest version of 2018 was a good year...

Caution! Vivado has had a habit in recent years of changing syntax for constraints and this can be a great source of confusion if you're reading constraints made for tool versions created for another version. Mostly though, older versions involve a considerably smaller install download.

Tool bugs are a problem for Intel, though for different reasons, and particularly for Windows versions. I tend to avoid the most recent versions of FPGA tools for most work because it's too much work discovering what new hellish surprises await me and having to figure out a solution. They need to figure out a better way to construct their software.