Diglent BASYS3 will not let me make a flip flop

[FPGAlearner]

I have been trying all day to make a simple flip flop with the BASYS 3 and Vivado.

This code below is correct. I have also used many other variations of this code, including Verilog instead of VHDL.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity first_flipflop is

Port ( D : in STD_LOGIC;

Clk : in STD_LOGIC;

Q : out STD_LOGIC);

end first_flipflop;



architecture Behavioral of first_flipflop is



begin

process(Clk)

begin

if(rising_edge(Clk)) then

Q <= D;

end if;

end process;

end Behavioral;

Constraint:

#LED

set_property PACKAGE_PIN V14 [get_ports Q]

set_property IOSTANDARD LVCMOS33 [get_ports Q]



#Button

set_property PACKAGE_PIN W19 [get_ports D]

set_property IOSTANDARD LVCMOS33 [get_ports D]



#Clock



set_property PACKAGE_PIN W5 [get_ports Clk]

set_property IOSTANDARD LVCMOS12 [get_ports Clk]

create_clock -add -name sys_clk_pin -period 10.00 -waveform (0 5) [get_ports Clk]

First, when I try to process the code it tells me that the clock cannot use LVCMOS33 even though when I watch people use this board for flip flops on YouTube they use the same clock W5 pin with LCVMOS33. So, to remove the error in the log I changed LVCMOS33 to LVCMOS12 or 18.

Then, when I try to process the new code it tells me that the i/o ports do not work with the clock pin with the IBUF error. Not knowing any other possibility for this exact circuit I want to make, I use the following to bypass this error:

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]

Finally, everything should be working now right? No. Now, it tells me I do not have my Q and D constraints(even though I clearly do) and when I go into the i/o ports for Q and D it forces them on two random pins that I do not want them to be on(I want D to be a button/switch and Q to be an LED). When I try to change these pins it literally does not let me, every time I change the pin in the box it just puts the same pin they put back in. This is the error it gives concerning this:

[DRC UCIO-1] Unconstrained Logical Port: 2 out of 4 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: d, and q.

At this point, I am exhausted and do not know if the circuit I want to build is even possible with my BASYS3. I just want to use a button/switch as D, the clock W5 pin as the clock, and an LED as a Q indicator. If anyone can help I would greatly appreciate it.
 

 

 

Edited September 6, 2022 by FPGAlearner

[zygot]

OK... Deep breath in... deep breath out...

First create a testbench and simulate the source code before creating a configuration file. All you need is your program VHDL source file and the testbench source file.

When you are ready to create a bitstream to dun on hardware you will need both the VHDL source file and a constraints file in your project. Here's where things get confusing. The syntax for your constraints depends on the version of the tools that you are using. In later versions of Vivado you have the option of setting the project to a device or a board for which it has board files. This can be a source of problems in recent versions of Vivado if you specify a board instead of a specific device in your project settings.

I suggest that you choose the specific device in your project settings rather than a board file for HDL development. Ideally, you might use the master constraints file for your board as a guide to creating a custom constraints file. You have the option of using the pin names in the master constraint file. If you do this then you can just use the master constraints .xdc file and comment out the unused pin assignments. You must then change the signal names on your toplevel entity port list to match the signal names in the
master constraint file. The other way to do this is to create a custom constraints file using the master constraints as a guide and using clk, D and Q as signal names. Just make sure that the entity for the toplevel file in your design matches the names of the constraints EXACTLY for either option,

I suggest checking pin location assignments with the schematic before trying to create a bitstream.

First run Synthesis in your tool. Before doing implementation look at the messages for warnings that your constraints were ignored for any reason. You will get warning messages if they are. In this case you need to figure out what the correct syntax for yoru tool version is. Vivado has a language template feature or you can use the TCL console to get more information. Until you can get past Synthesis without any messages indicating that any of your constraints were ignored ther's no point doing implementation or bitgen.

You problems have noting to do with the target board or device; just a problem communicating with the tools.

[JColvin]

Hi @FPGAlearner,

I agree with what @zygot said, in particular the line about "Just make sure that the entity for the toplevel file in your design matches the names of the constraints EXACTLY"; presuming you copied the error code verbatim, this is one source of error that I would be eyeing the most, along with finding out what FPGA device Vivado currently thinks it is working with.

Thanks,
JColvin

P.S. I can easily generate a bitstream for the Basys 3 with the code you provided in the block quote verbatim (albeit with the clock set to LVCMOS33 since the bank that pin is connected to on the Basys 3  (Bank 34) is powered at 3.3 V as per the schematic: https://digilent.com/reference/_media/reference/programmable-logic/basys-3/basys-3-sch-public-rev-d.pdf)

[FPGAlearner]

16 hours ago, zygot said:

OK... Deep breath in... deep breath out...

First create a testbench and simulate the source code before creating a configuration file. All you need is your program VHDL source file and the testbench source file.

When you are ready to create a bitstream to dun on hardware you will need both the VHDL source file and a constraints file in your project. Here's where things get confusing. The syntax for your constraints depends on the version of the tools that you are using. In later versions of Vivado you have the option of setting the project to a device or a board for which it has board files. This can be a source of problems in recent versions of Vivado if you specify a board instead of a specific device in your project settings.

I suggest that you choose the specific device in your project settings rather than a board file for HDL development. Ideally, you might use the master constraints file for your board as a guide to creating a custom constraints file. You have the option of using the pin names in the master constraint file. If you do this then you can just use the master constraints .xdc file and comment out the unused pin assignments. You must then change the signal names on your toplevel entity port list to match the signal names in the
master constraint file. The other way to do this is to create a custom constraints file using the master constraints as a guide and using clk, D and Q as signal names. Just make sure that the entity for the toplevel file in your design matches the names of the constraints EXACTLY for either option,

I suggest checking pin location assignments with the schematic before trying to create a bitstream.

First run Synthesis in your tool. Before doing implementation look at the messages for warnings that your constraints were ignored for any reason. You will get warning messages if they are. In this case you need to figure out what the correct syntax for yoru tool version is. Vivado has a language template feature or you can use the TCL console to get more information. Until you can get past Synthesis without any messages indicating that any of your constraints were ignored ther's no point doing implementation or bitgen.

You problems have noting to do with the target board or device; just a problem communicating with the tools.

Thank you for this. I figured it out finally. I kept getting this after synthesis:

WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.

And I looked up a solution and had to type this into the TCL console: write_checkpoint synth.dcp