Question about XADC application on Arty A7-100T

[tian]

I have an Arty A7-100T. My project is to read the A0 to A5 analog inputs into the MicroBlaze microprocessor and send it out via UART.

I was firstly trying to use XADC IP to convert the Analog to Digital without the MicroBlaze yet. However, I can never read the correct data from A0 to A5. Please see the following screenshots as the configuration (currently configured as A0 and A1 channels only). Tried many different combinations without any correct results. So have to ask someone here to help. 

From the warning message in the implementation, looks like it is because the VP/VN Pins are not assigned properly. Can someone give me some hints or experiences on how should I assign these pins to make it work, that is, the A0 to A5 channels connected to the real ADC inside the FPGA? Thanks so much. 

 

[JColvin]

Hi @tian,

The reason you are running into issues is because vauxp0/vauxn0 and vauxp1/vauxn1 are not the A0 and A1 pins on Arty A7 100.

The channel number differences are a little wonky admittedly, but the table at the end of the Arty A7 Reference Manual tells you which pin on the shield connector is associated with which vaux channel number on the Artix FPGA, https://digilent.com/reference/programmable-logic/arty-a7/reference-manual#shield_analog_io. So, for example if you want to use A0 and A1 as single ended analog inputs, you would need to enable vauxp4/vauxn4 & vauxp5/vauxn5, respectively.

The .xdc for the Arty A7 may be a bit easier to read in terms of pin assignment, https://github.com/Digilent/digilent-xdc/blob/master/Arty-A7-100-Master.xdc#L120; it looks like you have the approach already with the making the pins external, you just ended up constraining them not to the correct pins.

For reference, V_P is located on J10 and V_N is located on K9. So their constraints would look something like:

#set_property -dict { PACKAGE_PIN J10    IOSTANDARD LVCMOS33 } [get_ports { Vp_Vn_0_v_p  }]; #VP_0 	   ChipKit pin=V_P
#set_property -dict { PACKAGE_PIN K9    IOSTANDARD LVCMOS33 } [get_ports { Vp_Vn_0_v_n  }]; #VN_0 	   ChipKit pin=V_N

Note however that this analog input pair, like the other analog input pairs, do not have any sort of voltage divider (like on the single ended inputs dividing from 3.3 V logic to 1.0 V) so the voltage difference applied needs to be within the allowed voltage range of 0 V to 1 V in unipolar mode and -0.5 V and +0.5 V in bipolar mode.

Let me know if you have any questions about this.

Thanks,
JColvin

[tian]

Someone can help on this question? Thanks so much. 

[jsobas]

Hello,

I think youre ports name in XDC (constraints) file are not the same in your Block Design.

May be try to change input name in your Block Design.

See you

Justin

[tian]

Thank you so much for JColvin's detailed explanation. That is the problem, and after I changed A0 and A1 to Aux4 and Aux5, the problem is solved. 

Edited September 9, 2022 by tian