How to Generate Device tree for Single core Cora Z7

[chaitusvk]

i am generating device tree with

" petalinux-create --type project --template zynq --name zybo_acu_linux"

and config with

" petalinux-config --get-hw-description ../zynq_acu/"

 

But ... In device tree i have cpu 1 , PTM and Funnel associated with CPU1 which is not physically present

    cpus {
    		#address-cells = <1>;
    		#size-cells = <0>;
     
    		cpu0: cpu@0 {
    			compatible = "arm,cortex-a9";
    			device_type = "cpu";
    			reg = <0>;
    			clocks = <&clkc 3>;
    			clock-latency = <1000>;
    			cpu0-supply = <&regulator_vccpint>;
    			operating-points = <
    				/* kHz    uV */
    				666667  1000000
    				333334  1000000
    			>;
    		};
     
    		cpu1: cpu@1 {
    			compatible = "arm,cortex-a9";
    			device_type = "cpu";
    			reg = <1>;
    			clocks = <&clkc 3>;
    		};
    	};
     
    ptm@f889d000 {
    			compatible = "arm,coresight-etm3x", "arm,primecell";
    			reg = <0xf889d000 0x1000>;
    			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
    			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
    			cpu = <&cpu1>;
    			out-ports {
    				port {
    					ptm1_out_port: endpoint {
    						remote-endpoint = <&funnel0_in_port1>;
    					};
    				};
    			};
    		};

please help me how to generate proper device tree ...for Single core Cora Z7 i am using petalinux 2021.2

[Marty Ryba]

He got a better answer in the Xilinx forum, since those files are auto-generated your edits will tend to disappear. Instead, you put this in your system-user.dtsi:

system-user.dtsi

[RyanW]

Hi, I had a similar problem using the Cora Z7-07S.

To make sure we're on the same page. I'm changing this in the file

$PETALINUX_PROJECT/components/plnx_workspace/device-tree/device-tree/zynq-7000.dtsi

I just commented out that reference to CPU1.

/*cpu1: cpu@1 {
    			compatible = "arm,cortex-a9";
    			device_type = "cpu";
    			reg = <1>;
    			clocks = <&clkc 3>;
    		};*/

And then replaced the reference to cpu1 with cpu0 in the PTM.

    ptm@f889d000 {
    			compatible = "arm,coresight-etm3x", "arm,primecell";
    			reg = <0xf889d000 0x1000>;
    			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
    			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
    			//cpu = <&cpu1>;
			cpu = <&cpu0>;
    			out-ports {
    				port {
    					ptm1_out_port: endpoint {
    						remote-endpoint = <&funnel0_in_port1>;
    					};
    				};
    			};
    		};

I'm not sure if that second PTM physically exists in this chip or not, but doing just this worked for me on my system. The ptm1 is referenced only in one other spot in my device tree, so I'm considering taking out the chain of references stemming from the cpu1 to ptm1. From what I can tell a PTM is A "Program Trace Macrocell (PTM) is a real-time trace module providing instruction tracing of a processor." so it would seem that is has something to do with tracking instructions in a debug mode or something inside the processor, and it would stand to reason there would be one per core, so the second one seems extraneous.

Edited December 1, 2022 by RyanW

[RyanW]

On 2/15/2023 at 8:48 AM, Marty Ryba said:

He got a better answer in the Xilinx forum, since those files are auto-generated your edits will tend to disappear. Instead, you put this in your system-user.dtsi:

system-user.dtsi 268 B · 6 downloads

Thanks for this. I figured there was probably some way to do this, but for the time being I just had to work with my cobbled together solution.