DDR3 memory interface with Zybo Board

[Prabhat.kumar]

Hi all,

I have got a Zybo board. I am trying to explore the SDRAM available on the board which turns out to be two of these MT41J128M16JT-125, arranged such that they the data lines become 32bit wide, giving a total of 512MB of memory.  While reading through the reference manual, it says that "The PS incorporates an AXI memory port interface, a DDR controller, the associated PHY, and a dedicated I/O bank. DDR3 memory interface speeds up to 533 MHz/1066 Mbps are supported¹."

However I think the 1066Mbps should be changed with 1066 MT/s. This is because the DDR RAM transfers data twice in each clock cycle. Please correct me here. I am a newbie in using DRAM with FPGAs, so it would great if you all elaborate a bit in the answer.

Thank you.

 

[zygot]

For a PHY clock of 533 MHz 1066 Mbps is correct in terms of the data rate per DQ pin. 1066 MT/s is also correct. The actual data rate depends on the width of the DQ data bus, so neither the Mbps or MT/s performance specification has much meaning without knowing the later.

I'm not sure what you mean by "exploring the SDRAM available on the board". It's possible to change the memory controller setting registers but this is not recommended. In general PL designs can DMA data to and from the PS external memory, or internal PS memory using the PS AXI infrastructure.Of course these memories can be used by applications running in the PS ARM cores. If both the ARM cores and the PL are sharing a memory resource there will be performance penalties.

Reading the board Reference Manual is great. Before trying to understand what you can do with your board you should read all of the relevant reference material associated with the ZYNQ FPGA device on you board as well as the documents related to using the programmable logic in its PL. Edited August 7, 2022 by zygot

[Prabhat.kumar]

15 minutes ago, zygot said:

For a PHY clock of 533 MHz 1066 Mbps is correct in terms of the data rate per DQ pin. 1066 MT/s is also correct. The actual data rate depends on the width of the DQ data bus, so neither the Mbps or MT/s performance specification has much meaning without knowing the later.

I'm not sure what you mean by "exploring the SDRAM available on the board". It's possible to change the memory controller setting registers but this is not recommended. In general PL designs can DMA data to and from the PS external memory, or internal PS memory using the PS AXI infrastructure.Of course these memories can be used by applications running in the PS ARM cores. If both the ARM cores and the PL are sharing a memory resource there will be performance penalties.

Reading the board Reference Manual is great. Before trying to understand what you can do with your board you should read all of the relevant reference material associated with the ZYNQ FPGA device on you board as well as the documents related to using the programmable logic in its PL.

Thank you, you cleared a big doubt for me. As far as exploring goes, I am trying to understand the standard DRAM interface in general with FPGAs. I have a image processing application in hand in which I am only supposed to use the PL part( hence I was using the Arty A7 earlier, but I had to return that board from who I borrowed.) I got a Zybo board from my college and knowing that the PL part of Zync devices is almost equivalent to Artrix7 devices, I started to learn about the SDRAM interface.

However seeing so much confusing terminology about the DRAM interface, I ended up here for which, I am grateful. 

Edited August 7, 2022 by Prabhat.kumar

[zygot]

External memory for devices like the on one the Arty-A7 will be completely different than for a ZYNQ based board like the ZYBO. There are very few ZYNQ-based boards with external memory connected to the PS and a separate external memory connected to the PL. You could use a MicroBlaze and AXI bus IP in an Arty-A7 video application, but this would consume a lot of resources, particularly BRAM.

The ZYNQ 7000 TRM is a good place to start reading.

FPGA vendors have had a bad habit of making some interfaces, like DDR memory, overly complicated and confusing. Dynamic memories are complicated all by themselves. As data rates get higher, so does the complexity.

[Prabhat.kumar]

10 hours ago, zygot said:

External memory for devices like the on one the Arty-A7 will be completely different than for a ZYNQ based board like the ZYBO. There are very few ZYNQ-based boards with external memory connected to the PS and a separate external memory connected to the PL. You could use a MicroBlaze and AXI bus IP in an Arty-A7 video application, but this would consume a lot of resources, particularly BRAM.

The ZYNQ 7000 TRM is a good place to start reading.

FPGA vendors have had a bad habit of making some interfaces, like DDR memory, overly complicated and confusing. Dynamic memories are complicated all by themselves. As data rates get higher, so does the complexity.

Please excuse my crudity in writing. As I mentioned before I am still quite new to FPGAs. I can see written in the reference manual that the DDR3 SDRAM is connected to the hard memory controller in the PS system. However, my doubt here is that whether the DDR3 is connected to the MIO banks or some generic ZYNQ chip pins? If its connected to the MIO banks, can I access them through the PL part ?

I was trying to skimp through some examples where MIG is used. But my doubt is, if the SDRAM is connected to the PS then, can’t I use the MIG or write my very simple SDRAM controller based on examples( obviously it will be much slower than the 1066 MT/s maximum)?

Also, say it’s not possible to interface the SDRAM directly from the PL then, what all options do I have ? My application as of now is to use a camera and apply some image processing algorithms like sobel edge detection etc., in a continuous live stream type on a VGA monitor.

Thank you.

Edited August 8, 2022 by Prabhat.kumar

[zygot]

There's no way to use the Mig or any other IP to allow your PL design direct control over memory controlled by the PS for ZYNQ devices. If you look at the schematic, what pins would you assign the DDR controller PHY to? There are none. The ZCU106 is one ZYNQ based board with a dedicated DDR memory connected to PL pins. I am unaware of any other such Xilinx board.

Your only choice, if you need to use external memory in your logic design, is to transfer data to and from PS memory via AXI infrastructure. I haven't done this but I believe that there are design examples to lead the way. For low resolution displays like VGA you can use Pl BRAM as a frame buffer and avoid using the PS DDR.

The original ZYBO has a VGA connector for low resolution video output and a single HDMI for output and, in theory input. Both interfaces are connected to PL pins.

Again, you need to have some understanding of what the ZYNQ device resources are as well as how your board is designed in order to make a usable design plan. If you are going to use a ZYNQ based device or soft-processor based deign, then you need to figure out how to partition your functionality between hardware and software as well.

There's a lot of information to consume but you can do what you want with the board available to you. Start with reading the documentation for your board and then ZYNQ related documentation It's not a trivial pursuit so you need to figure out how to scan through all of the basic documentation and concentrate on the pertinent stuff. Edited August 8, 2022 by zygot

[Prabhat.kumar]

1 hour ago, zygot said:

There's no way to use the Mig or any other IP to allow your PL design direct control over memory controlled by the PS for ZYNQ devices. If you look at the schematic, what pins would you assign the DDR controller PHY to? There are none. The ZCU106 is one ZYNQ based board with a dedicated DDR memory connected to PL pins. I am unaware of any other such Xilinx board.

Your only choice, if you need to use external memory in your logic design, is to transfer data to and from PS memory via AXI infrastructure. I haven't done this but I believe that there are design examples to lead the way. For low resolution displays like VGA you can use Pl BRAM as a frame buffer and avoid using the PS DDR.

The original ZYBO has a VGA connector for low resolution video output and a single HDMI for output and, in theory input. Both interfaces are connected to PL pins.

Again, you need to have some understanding of what the ZYNQ device resources are as well as how your board is designed in order to make a usable design plan. If you are going to use a ZYNQ based device or soft-processor based deign, then you need to figure out how to partition your functionality between hardware and software as well.

There's a lot of information to consume but you can do what you want with the board available to you. Start with reading the documentation for your board and then ZYNQ related documentation It's not a trivial pursuit so you need to figure out how to scan through all of the basic documentation and concentrate on the pertinent stuff.

Thank you very much. I was thinking of using the built in DMA controller to transfer data to and fro from the memory to the PL section without the use of the PS section. Out of the 8 channels, 4 can be used by the PL and rest 4 by the PS. What do you think about this approach.

I guess it was a bad idea going with a ZYNQ based board since I dont even a good experience with normal PL( apart from few simple camera projects, on which I used BRAM), forget doing SoC like stuff with ZYNQ. There are no examples which I can't directly look up to for using the DMA, DRAM, things, which I would expect digilent to do.

I had done the camera and display interface with a QVGA display and hence BRAM was sufficent to store 1 frame. However for image processing I need atleast two frames plus some extras for FIFOs, so that for sure isn't happening with the XC7Z010 model of the ZYBO board which I have. 

I have access to SPARTAN 6 boards, but again I think ISE isn't as convenient as vivado. 

Edited August 8, 2022 by Prabhat.kumar

[zygot]

Please read carefully through UG585 the ZYNQ 7000 series TRM.

The PS has a DMA controller, and I've used it, but it's not of much use if there's no data path between the PS and PL. At some point, if you want to use the PS DDR, or you want an ARM core to have access to a PL video frame buffer, then you will have to have some AXI IP in your PL logic connected to either one of the fabric masters ports or slave AXI ports.

The Z7010 isn't very resource rich but it might be possible to implement your project without much interaction from the PS if your video frame buffer can be small enough, and your video resolution is low enough. I don't know if the HDMI interface on the original ZYBO is all that usable. Digilent has improved upon HDMI interface design in more recent products. The Z7020 is roughly equivalent to an A75 device in terms of resources.

I still use ISE on Win10 for ATLAS based projects. In some specs that is a better video platform to work with than low end Artix based devices. The Spartan family did not have nearly the BRAM resources that the Series 7 devices have though. Personally, I usually opt to do development with ISE on my aging Win7 box where everything works as intended. I guess that you have some tough decisions to make before thinking about how you might do about implementing your project. Video depth and resolution will likely be a driving factor in that process. Edited August 8, 2022 by zygot

[Prabhat.kumar]

3 hours ago, zygot said:

Please read carefully through UG585 the ZYNQ 7000 series TRM.

The PS has a DMA controller, and I've used it, but it's not of much use if there's no data path between the PS and PL. At some point, if you want to use the PS DDR, or you want an ARM core to have access to a PL video frame buffer, then you will have to have some AXI IP in your PL logic connected to either one of the fabric masters ports or slave AXI ports.

The Z7010 isn't very resource rich but it might be possible to implement your project without much interaction from the PS if your video frame buffer can be small enough, and your video resolution is low enough. I don't know if the HDMI interface on the original ZYBO is all that usable. Digilent has improved upon HDMI interface design in more recent products. The Z7020 is roughly equivalent to an A75 device in terms of resources.

I still use ISE on Win10 for ATLAS based projects. In some specs that is a better video platform to work with than low end Artix based devices. The Spartan family did not have nearly the BRAM resources that the Series 7 devices have though. Personally, I usually opt to do development with ISE on my aging Win7 box where everything works as intended. I guess that you have some tough decisions to make before thinking about how you might do about implementing your project. Video depth and resolution will likely be a driving factor in that process.

Can you please elaborate a bit on the fact that DMA controller is not much useful in this case. I am willing to use the AXI interface so that DMA can send me the data from the DDR memory via the PS memory controller. And also I cant go below 8 bits of resulution in VGA mode also, else it will be shame for such a powerful FPGA device. 

All I want to know whether for the DMA to work properly, is it neccasary for me to use the PS section. I think for configuring the DMA, we need to use the PS section and do some C coding. I am not against it, but I wanted to keep this project on hardware (PL part) as much as possible. This is so that later it can be made to work on some lower end FPGA also maybe.

I have nothing against ISE, its just the fact that I have got used to vivado a bit now. Shifting to ISE will cost me time and effort to understand its interface, and also the fact we have to use a different programmer unlike vivado, where everything is in one.

Edited August 8, 2022 by Prabhat.kumar

[zygot]

The PS contains a PL330 DMA Controller that can move data from any address accessible to the cores. It's possible to provide addressable connections to logic in the PL though AXI bus IP. For instance you can add an AXI BRAM controller and dual port BRAM ( resides in the PL ) in such a way that the cores can read or write to it as well as the logic in your PL. This is a fairly simple and straight-forward way to pass data between the PL and the cores. If you have a lot of data that you want to transfer between the PL and memory that the PS controls, like DDR, there are other AXI IP that implement DMA in logic without PS intervention. The BRAM Controller provided with Vivado is limited to 8KB but you can implement many iterations to achieve a larger size.

I would think that it's quite possible to implement, say a VGA 680x800 8-bit frame buffer in BRAM and do everything that you want to do in logic. It's a matter of scale and what you want to demonstrate. The PS might not even have much involvement, depending on how you do your processing. There are a lot free video related AXI IP that comes with Vivado that might be of interest so there isn't one ideal way to implement a particular design. I don't want to steer you in any particular direction. The unfortunate thing about using the free IP that comes with Vivado is that they come and go from tool version to tool version. Also, FPGA vendors have a bad habit of breaking IP from previous tool versions. The only alternative is to write your own AXI master or slave. I wouldn't recommend that for anyone without a lot of AXI design experience.

Look around. I'm sure there is a similar project published for your board.

When using Windows I usually use Digilent's Adept Utility to configure FPGA boards as it can be less of a hassle than Vivado Hardware Manager... especially if I have multiple boards in a design, which happens frequently. I really never was friends with the ISE Impact programming facility.

[Prabhat.kumar]

1 hour ago, zygot said:

The PS contains a PL330 DMA Controller that can move data from any address accessible to the cores. It's possible to provide addressable connections to logic in the PL though AXI bus IP. For instance you can add an AXI BRAM controller and dual port BRAM ( resides in the PL ) in such a way that the cores can read or write to it as well as the logic in your PL. This is a fairly simple and straight-forward way to pass data between the PL and the cores. If you have a lot of data that you want to transfer between the PL and memory that the PS controls, like DDR, there are other AXI IP that implement DMA in logic without PS intervention. The BRAM Controller provided with Vivado is limited to 8KB but you can implement many iterations to achieve a larger size.

I would think that it's quite possible to implement, say a VGA 680x800 8-bit frame buffer in BRAM and do everything that you want to do in logic. It's a matter of scale and what you want to demonstrate. The PS might not even have much involvement, depending on how you do your processing. There are a lot free video related AXI IP that comes with Vivado that might be of interest so there isn't one ideal way to implement a particular design. I don't want to steer you in any particular direction. The unfortunate thing about using the free IP that comes with Vivado is that they come and go from tool version to tool version. Also, FPGA vendors have a bad habit of breaking IP from previous tool versions. The only alternative is to write your own AXI master or slave. I wouldn't recommend that for anyone without a lot of AXI design experience.

Look around. I'm sure there is a similar project published for your board.

When using Windows I usually use Digilent's Adept Utility to configure FPGA boards as it can be less of a hassle than Vivado Hardware Manager... especially if I have multiple boards in a design, which happens frequently. I really never was friends with the ISE Impact programming facility.

Thanks again. I will have to study about the DMA controller and in general the ZYNQ now, as without that it’s almost impossible to understand what things I can use to do my project. I am thinking of using the ZYNQ book as a reference. If you have any other suggestion then please let me know.

As I said before, I managed to display just a live stream video on a QVGA TFT on a Arty A7 board. 

In 8 bits mode, I was able to fit atmost two frame, consuming 80% of BRAM. 
As the PL of the ZYNQ is almost equivalent to ARTIX 7 series, I am sure the same will be the case here. Also then I will have to use 2 new FIFOs now, which I think isn’t going to fit or maybe just barely fit.

And the fact that ZYBO has 16 bit VGA, makes every want to stick to the 16 bit mode itself and use the DDR for the storage. This will leave BRAM empty for some other critical operations.