25MHz or 125MHz PL reference clock on Genesys ZU-3EG

[MaxPof]

Hi everyone,

 

I want to use a reference clock on the PL side on my Genesys ZU-3EG rev. B.

The constraint file gives a 125 MHz clock on the E12 pin but the reference manual says that it's a 25MHz clock.

Which one is correct?

Is it possible to have a 125MHz PL clock on Genesys as there is on the K17 pin of the Zybo?

Thanks!

[elodg]

The reference manual listing 25 MHz is correct. The comment in the xdc file was incorrect, which is now fixed and pushed to Github.

You can use Clocking Wizard in the FPGA to generate 125 MHz or configure the Ethernet PHY over MDIO to output 125 MHz on the sysclk port. 

Edited July 27, 2022 by elodg