MaxPof

Hi everyone, I want to use a reference clock on the PL side on my Genesys ZU-3EG rev. B. The constraint file gives a 125 MHz clock on the E12 pin but the reference manual says that it's a 25MHz clock. Which one is correct? Is it possible to have a 125MHz PL clock on Genesys as there is on the K17 pin of the Zybo? Thanks!

Through the HP0 port, right? Alright perfect, that what I want to do! Yeah I don't know, it's just very unclear how to access DDR with PS (let's leave the PL aside for the moment) With Zynq, you have a DDR port which appears when you enable DDR. That's not the case with Ultrascale. So I thought I should add the DDR block... Ok ok, so, same as Zynq, all is PS handled, so no need for the DDR bloc. Yes, sorry. My question was more about how to interface the DDR because I thought is was way more complicated. But I'm not very clear. What I do on my zybo is: Access DDR from PS ( from my application on the ARM) and access from HLS IP through AXI/HP0 interface. So I think you resolve my problem if you say that I just have to enable the DDR in the Ultrascale config to make it works the same way. I was just going on something much more complicated since the DDR port does not appear on the BD... Thanks for your answer!

Hi! Yes, sorry I wasn't clear, this is what I do. See here the method that I use for Zybo. So yeah, my problem is not so much the PS/PL part, but just to be able to connect the DDR to my BD. So I don't have to use the MIG on my bloc diagram? I attach a screenshot of my actual (cleaned) BD

Hi everyone, I'm sorry, this post is basically the same that the one I've posted on Xilinx's forum. I was waiting to be approved on this forum for days and I really needed to move forward... But this question is way better suited here. So I would like to be able to access the DDR on both the PL and PS side. I already did it for the zybo but I have a lot of trouble with the Genesys ZU 3EG. Here’s where I stand: -I've added the Genesys boards files in Vivado -I've created the BD, added the Ultrascale Mpsoc bloc and enabled DDR Q: How do I know that the default configuration for DDR is OK? Is it already configured in the Genesys boards files? Or should I change something. -I've added the DDR4 MIG Q: I have no clue how to configure that... -Run Connection Automation Q: Connection automation create a diff clock at 100MHz on the BD for the C0_SYS_CLK port of the MIG, which is not coherent with the default 70.1361MHz needed. Should I adapt the 100MHz? Q: Should I define this diff clock that the MIG needs in my constraint file? -Run synthesis: OK -Run Implementation: return this error: [Mig 66-99] Memory Core Error - [memory/ddr/u_ddr4_0] Either port(s) c0_sys_clk_p, c0_sys_clk_n is/are not placed or un-supported clocking structure/circuit for memory ip instance. Please refer to clocking section of PG150 for supported clocking structures. [Mig 66-99] Memory Core Error - [memory/ddr/u_ddr4_0] Port(s) c0_ddr4_ck_c[0],c0_ddr4_ck_t[0],c0_ddr4_adr[0],c0_ddr4_adr[1],c0_ddr4_adr[2],c0_ddr4_adr[3],c0_ddr4_adr[4],c0_ddr4_adr[5],c0_ddr4_adr[6],c0_ddr4_adr[7],c0_ddr4_adr[8],c0_ddr4_adr[9],c0_ddr4_adr[10],c0_ddr4_adr[11],c0_ddr4_adr[12],c0_ddr4_adr[13],c0_ddr4_adr[14],c0_ddr4_adr[15],c0_ddr4_adr[16],c0_ddr4_ba[0],c0_ddr4_ba[1],c0_ddr4_bg[0],c0_sys_clk_n,c0_sys_clk_p,c0_ddr4_bg[1],c0_ddr4_cs_n[0],c0_ddr4_cke[0],c0_ddr4_odt[0],c0_ddr4_act_n,c0_ddr4_reset_n,c0_ddr4_dqs_c[0],c0_ddr4_dqs_t[0],c0_ddr4_dm_dbi_n[0],c0_ddr4_dq[0],c0_ddr4_dq[1],c0_ddr4_dq[2],c0_ddr4_dq[3],c0_ddr4_dq[4],c0_ddr4_dq[5],c0_ddr4_dq[6],c0_ddr4_dq[7],c0_ddr4_dqs_c[2],c0_ddr4_dqs_t[2],c0_ddr4_dm_dbi_n[2],c0_ddr4_dq[16],c0_ddr4_dq[17],c0_ddr4_dq[18],c0_ddr4_dq[19],c0_ddr4_dq[20],c0_ddr4_dq[21],c0_ddr4_dq[22],c0_ddr4_dq[23],c0_ddr4_dqs_c[3],c0_ddr4_dqs_t[3],c0_ddr4_dm_dbi_n[3],c0_ddr4_dq[24],c0_ddr4_dq[25],c0_ddr4_dq[26],c0_ddr4_dq[27],c0_ddr4_dq[28],c0_ddr4_dq[29],c0_ddr4_dq[30],c0_ddr4_dq[31],c0_ddr4_dqs_c[4],c0_ddr4_dqs_t[4],c0_ddr4_dm_dbi_n[4],c0_ddr4_dq[32],c0_ddr4_dq[33],c0_ddr4_dq[34],c0_ddr4_dq[35],c0_ddr4_dq[36],c0_ddr4_dq[37],c0_ddr4_dq[38],c0_ddr4_dq[39],c0_ddr4_dqs_c[5],c0_ddr4_dqs_t[5],c0_ddr4_dm_dbi_n[5],c0_ddr4_dq[40],c0_ddr4_dq[41],c0_ddr4_dq[42],c0_ddr4_dq[43],c0_ddr4_dq[44],c0_ddr4_dq[45],c0_ddr4_dq[46],c0_ddr4_dq[47],c0_ddr4_dqs_c[6],c0_ddr4_dqs_t[6],c0_ddr4_dm_dbi_n[6],c0_ddr4_dq[48],c0_ddr4_dq[49],c0_ddr4_dq[50],c0_ddr4_dq[51],c0_ddr4_dq[52],c0_ddr4_dq[53],c0_ddr4_dq[54],c0_ddr4_dq[55],c0_ddr4_dqs_c[7],c0_ddr4_dqs_t[7],c0_ddr4_dm_dbi_n[7],c0_ddr4_dq[56],c0_ddr4_dq[57],c0_ddr4_dq[58],c0_ddr4_dq[59],c0_ddr4_dq[60],c0_ddr4_dq[61],c0_ddr4_dq[62],c0_ddr4_dq[63],c0_ddr4_dqs_c[1],c0_ddr4_dqs_t[1],c0_ddr4_dm_dbi_n[1],c0_ddr4_dq[8],c0_ddr4_dq[9],c0_ddr4_dq[10],c0_ddr4_dq[11],c0_ddr4_dq[12],c0_ddr4_dq[13],c0_ddr4_dq[14],c0_ddr4_dq[15] is/are not placed. Assign all ports to valid sites. The Digilent Reference Manual provide this link: https://support.xilinx.com/s/article/75768?language=en_US I tried to do what is said in "Enabling Dynamic DDR Configuration", but without any success. I try to follow this: https://support.xilinx.com/s/question/0D52E00006hpgtFSAQ/memory-core-error?language=en_US I've checked the DDR IO pins and they are not assigned. But if I refer to the schematic: https://digilent.com/reference/_media/reference/programmable-logic/genesys-zu/genesys_zu-3eg_revd1_sch_public.pdf I can't select the corresponding pins (e.g. W28 for DDR4_ADDR0 is not available). So I suppose the user don't have to assigne them. But I'm quite lost now... I saw that there was a MIG file for Genesys 2 that does the pin assignement, but nothing for Genesys ZU Has anyone ever got DDR working on Genesys ZU? (Not Genesy 2!) Thanks