About Basys 2 Analog Input Frequency Dividing

[noelani2306]

Hello everyone! Hope this message finds you well.

Before, I worked quite a lot on dividing frequencies of incoming digital signals, and this can be realized easily using counter registers in Verilog HDL, but now my task is to divide the frequency of the incoming analog signal which looks as a triangular wave. I have soldered the incoming signal to the PMOD Connectors on the FPGA board, but I am not sure whether I can trigger the main activity using positive edge of the signal as the signal is the analog one. How can I approach the problem?

 

Any help would be appreciated! Thanks!

 

[JColvin]

Hi @noelani2306,

The good news is that in principle you can still use the same method as with the digital signals with regards to the frequency dividing as analog signals will also reach the "logic high" and "logic low" voltage levels as well as positive and negative edges since the latter are effectively just comparing the current logic level to the previous logic level and determining if the signal went "positive" or "negative".

The large catch with analog signals being analyzed like a digital signal comes with how the 'logic high' and 'logic low' regions of digital logic standards are defined.  Since there are some "undefined" regions (i.e. regions that are outside the Input/Output High Level voltage and the Input/Output Low Level voltage) for each digital standard (I'm presuming you are using a 3.3 V standard), there is some ambiguity about whether or not the measured signal will be measured as.

There is a voltage threshold point for each logic standard where the device will switch it's interpretation of if the signal voltage is determined as "high" or "low", which is 1.5V for 3.3 V standards. You can learn more about the voltage standards here on this page, http://www.interfacebus.com/voltage_threshold.html, with a reference image for the 3.3 V logic standard voltage levels available here in Figure SB3 https://www.eetimes.com/a-brief-recap-of-popular-logic-standards/, (though the text on that page doesn't seem very helpful/well formatted).

That all being said, there isn't a way to directly determine the peak or valley of a triangle wave via a digital input. While the transition point is at 1.5 V, the logic inputs will not register an actual change until the signal increases to a 2.0 V level (the minimum Input High Voltage to register a logic high) or when the signal decreases to 0.8 V (the maximum Input Low Voltage to register a logic low). If the incoming triangle is a consistent frequency and is at 50% symmetry, I suppose it would be possible to do some additional math to calculate the theoretical locations of the peaks and valleys based on those points, but it would not be easy (and the straightforward math goes out the window as soon as the incoming triangle wave is not periodic/consistent).

Thanks,
JColvin

[robfinch]

It sounds to me like the OP is trying to replicate an incoming waveform at half frequency. I have not used this before, but could not the triangle wave be fed into the analog input ports of the FPGA, measured with XADC component, recorded then output at one half the rate? A delta-sigma DAC could be used for output.

[JColvin]

Hi @robfinch,

Normally yes, but unfortunately the Basys 2 with it's Spartan 3 chip does not have an XADC port available to users (at least best as I can tell from the schematic and reference manual; the Basys 2 had already been phased out in favor of Basys 3 by the time I joined Digilent, so I have never personally used the board).

To your point though, @noelani2306 could use some sort of analog to digital converter (such as the Pmod AD1) to more easily determine the peaks and valleys of the triangle wave and then output the signal through a digital to analog converter (such as the Pmod DA2, or any number of other ADCs or DACs that also exist out the world).

Thanks,
JColvin