I am using a Digilent Arty S7 board connected to a small serial EEPROM on another board using standard 2-wire IIC bus (SDA and SCL lines). I am using a Xilinx AXI IIC core in block design in Vivado 2022.1 and am having trouble connecting the SDA and SCL lines to external pins. I am hoping someone can tell me how to do this. I know that the SDA and SCL lines need to be open-drain, and I think the Xilinx primitive for this is OBUFT or possibly IOBUF. But I can't find either one of these in any IP to add to my block design. I did find IOBUFDS in the utility buffer IP, but I need single ended.
I also know that I need external pullup resistors. I just don't know how to implement open-drain within the context of a Vivado block design.
I have seen some discussion about modifying the wrapper file, but I want to let Vivado to manage the wrapper so it can change automatically when I change my design. Any help is appreciated.
Question
Jim Brady
Hello ---
I am using a Digilent Arty S7 board connected to a small serial EEPROM on another board using standard 2-wire IIC bus (SDA and SCL lines). I am using a Xilinx AXI IIC core in block design in Vivado 2022.1 and am having trouble connecting the SDA and SCL lines to external pins. I am hoping someone can tell me how to do this. I know that the SDA and SCL lines need to be open-drain, and I think the Xilinx primitive for this is OBUFT or possibly IOBUF. But I can't find either one of these in any IP to add to my block design. I did find IOBUFDS in the utility buffer IP, but I need single ended.
I also know that I need external pullup resistors. I just don't know how to implement open-drain within the context of a Vivado block design.
I have seen some discussion about modifying the wrapper file, but I want to let Vivado to manage the wrapper so it can change automatically when I change my design. Any help is appreciated.
Thanks,
Jim
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