Jim Brady

Hello --- I am using a Digilent Arty S7 board connected to a small serial EEPROM on another board using standard 2-wire IIC bus (SDA and SCL lines). I am using a Xilinx AXI IIC core in block design in Vivado 2022.1 and am having trouble connecting the SDA and SCL lines to external pins. I am hoping someone can tell me how to do this. I know that the SDA and SCL lines need to be open-drain, and I think the Xilinx primitive for this is OBUFT or possibly IOBUF. But I can't find either one of these in any IP to add to my block design. I did find IOBUFDS in the utility buffer IP, but I need single ended. I also know that I need external pullup resistors. I just don't know how to implement open-drain within the context of a Vivado block design. I have seen some discussion about modifying the wrapper file, but I want to let Vivado to manage the wrapper so it can change automatically when I change my design. Any help is appreciated. Thanks, Jim

Hello, I have an Arty S7 board and would like to read and write a small region (say 256 bytes) of SPI flash from my MicroBlaze program. I assume I would create an AXI quad SPI core, attached to the MicroBlaze design, and connect it to the same pins used for configuration. I have a some questions : Is this even possible? After FPGA startup configuration is done, does the FPGA free up the SPI lines for such use? (I noticed some mention about the SCK line not being freed up.) What part of SPI flash does Vitis/Vivado write FPGA configuration into? (low-end, high-end, some settable region) Is there any MicroBlaze example code available? Is this so complex that I would be better off just using a small I2C EEPROM for my needs? Thanks for the help, Jim