Connecting IIC SDA and SCL lines to external pins

[Jim Brady]

Hello ---

I am using a Digilent Arty S7 board connected to a small serial EEPROM on another board using standard 2-wire IIC bus (SDA and SCL lines). I am using a Xilinx AXI IIC core in block design in Vivado 2022.1 and am having trouble connecting the SDA and SCL lines to external pins.  I am hoping someone can tell me how to do this. I know that the SDA and SCL lines need to be open-drain, and I think the Xilinx primitive for this is OBUFT or possibly IOBUF. But I can't find either one of these in any IP to add to my block design. I did find IOBUFDS in the utility buffer IP, but I need single ended.

I also know that I need external pullup resistors. I just don't know how to implement open-drain within the context of a Vivado block design.

I have seen some discussion about modifying the wrapper file, but I want to let Vivado to manage the wrapper so it can change automatically when I change my design. Any help is appreciated.

Thanks,

Jim

[artvvb]

Hi @Jim Brady

You could potentially use the Pmod Bridge IP core in our vivado-library repository to wire an AXI IIC core to a Pmod port and set up some internal pullups (note you'd need version 1.1 of the core).

The following is similar to the way that the Pmod Bridge handles it: Make the entire IIC interface external, then constrain the associated _io ports that get inferred - check the HDL wrapper for their specific names. IOBUFs ought to be inferred. Then you can use pull type constraints with these _io ports in your XDC file to enable some internal pullups in their buffers. I've attached a couple of screenshots of this, below.

Alternatively, to avoid the inferred stuff, you could write a custom RTL module that instantiates IOBUF primitives directly and add it to your block design.

Thanks,

Arthur

 

Block design with an external IIC interface

 

Wrapper including inferred IOBUFs

set_property -dict {PULLUP TRUE} [get_ports out2_T]

Sample line of an XDC enabling pullups