Need help in configuring audio codec chip in digilent anvyl board

[gp_1308]

Hello,

      I am working on a project, in which i need to do the following tasks:

       taking voice input from microphone->apply ADC->perform cross-correlation with audio file stored previously. 

I am beginner in FPGA programming. I have digilent anvyl board.

So my question is: How can i configure I2S codec present on the board? Shall i design small controller in FPGA to configure the audio codec chip?(I am assuming all pins of codec chip is connected to FPGA I/O.)

I have checked the demo project on audio codec but i couldn't understand  the code written there or project structure in general.

I really appreciate it if some one tell me how to proceed or provide some resource materials.

Cheers,

gp

[D@n]

Wow, for a starter project you did not pick an easy one.  May I suggest that there's a reason the audio example is the last chapter in the series of demonstration projects?  Have you worked your way through the simpler projects first?  That would be my suggestion.  Hopefully when you've gotten that far you will then understand the various project structures, what their components are, and why the various parts and pieces of a project exist.

I know from my own standpoint, I followed a similar progression both to learn about FPGA's and to start with any new board: the first step is always to get the various lights, switches, and buttons working.  The second step (for me at least) is trying to build a richer means of accessing the board and controlling it from a host computer (PC).  These are both very difficult challenges in themselves, although you will easily find many examples of people who have solved them.  Even with new boards (and I just got a new one) I'm still repeating these exercises: my first project turns a light on, the second project turns it off, the third project makes it blink, the fourth project uses the light to tell me if something else internal to the design is working and so on and so forth.

My next projects were more complex: getting the seven segment display to work, a VGA controller, reading and writing SPI flash, and so on and so forth.  Each project, especially for a beginner, should be slightly more complex than the last one.  Some of the most complex projects I've done include building an SDRAM memory interface and a CPU.  (Xilinx will provide both for you, if you would rather.)  Still, once you get there that leaves you with choices: do you wish to use a CPU within your FPGA?  Can you write programs for it?  How will the CPU interact with your audio port?

My point is, you may wish to work your way up from some very simple designs up to the point where you can understand the audio example design Digilent provided.

Of course, if you think I'm off base, that you're ready to dive right into the deep end and so forth, then go for it.  You might want the specification sheet for the audio chip on the Anvyl while you are at it as well.  That'll help you understand what needs to be done to read audio from the ADC.  The correlator you wish to write will also be an adventure--but I still suggest you take one step at a time.

Yours,

Dan

[D@n]

I did manage to find an Open Source i2s controller, if that'll help.  I'm often amazed at what I can find on oen cores.

 

Dan

[gp_1308]

Hello Dan,

          I totally agree with your suggestion that beginner should begin from the beginning. But i am not exactly beginner(should have mentioned in the question). Previously i have done some work in digital design but only simulation,not implemented those on FPGA(big mistake on my part). This work i am doing is part of course work and we have already showed virtual prototype using matlab simulink and so i have no choice,no going back now . Since i am running out of time hence thought of asking for some inputs in this forum. 

Today i had gone through spec sheet of codec on the board and was planning to implement FSM in FPGA to control the codec. Now the link you have provided for i2s controller is really going to help me. wishbone bus protocol is used in that core, that's new for me. I was thinking of using I2C protocol to control the chip, looks simple, that was mentioned in the spec sheet.  May be i can modify the core and implement as i want right? at least i can use it for reference. I am not implementing CPU in FPGA. I need to figure it out on implementing the cross-correlation operation in FPGA. I really hope i can pull this off.

Thanks again,

gp

 

[D@n]

Ok, no problem, I was just worried when you stated: "i couldn't understand the code written there or project structure in general."

As for simulation versus real FPGA, well, it depends upon your level of simulation.  I came across some code recently that would simulate the DWT within a JPEG encoder, and knew someone who needed that.  The simulation, though, didn't come with full access to all that you would need to do it: there was no memory controller, no memory bus, no means of getting information on and off the board, etc.  All of the things that you have to do to really do a project were missing.  That's experience number one with the difference.  Experience number two with the difference is that my simulations never set the defaults up to what the chip sets them to be.  Sure, if you specifiy initial values they will match, but any lack of specificity and the two didn't match.  Just some things to be aware of from my own experience.

Wishbone has become second nature to me, AXI not so much.  The wishbone spec can easily be found here, but I personally find the timing diagrams on pages 37, 42, 46, 49, 51, and 55 of that spec to be the most useful.  (Why anyone would want to use the classic mode and take three clocks to transmit what could be done in one is beyond me ...)  If the core claims wishbone compliance, then it's supposed to come with a specification and table within that specification describing that compliance.  I have no experience with the I2S core I pointed you at, other than to know that it is there--so I can't comment on how useful it may or may not be.

Cross correlation, though, hmm ... lots of choices there.  Conceptually its really simple.  On paper it looks easy.  Within an FPGA, you are going to have to take careful control of your multiplies and schedule them wisely.  Still, at audio rates, you have lots of options.

Sounds like a fun project.  When's the due date?

Dan

[gp_1308]

I will go through the wishbone spec to fit this in my project. Due date is in 15 days. 

After reading your first post, one more question came into my mind.(Atleast it's relevent to my project, if not for this question)

If i implement CPU in FPGA, then cross-correlation realization will be comparatively easy, because i can write code in C  and compile it and run on CPU. Am i right here? (Assuming soft core is readily available). I am just curious to find out other possibilities. I know this method is not for my level at present.

[D@n]

I'm not sure the benefits of using a CPU are as clear as you present them ....

A CPU will slow your correlation down, as you will be unable to run one (or more) multiplies per clock.  Depending on the length of the waveform you are trying to match, this may be a killer.  Remember, there is often a reason why you are writing HDL for an FPGA.  If your reason was blazing fast speed, you may lose that advantage by incorporating a CPU.

There's also a learning curve associated with getting a CPU running, having it properly connected to your logic, and debugging it.  While all doable, these skills aren't the same as the HDL skills you've been working with.

That said, if you had the time, I'd highly encourage you to try it and see if it works.  I just wouldn't encourage you to try it until you had something working that you could turn in.

Dan

P.S. Many soft cores are available, all with varying levels of support--it just depends upon your needs, what you wish to accomplish, and so forth.

[gp_1308]

Ok. Yes, i need to get some result first, later i can look for other options. Thanks a lot for all the guidance. 

[D@n]

Here's another twist for you: are you using an FFT?  You "should" be able to run a larger correlator for the same number of multiplies if you use an FFT.

If you don't know what an FFT is, you might wish to look this concept up, since as an instructor I would ask you about it.

If you do know what an FFT is, and find the idea fascinating, Xilinx CoreGen has an FFT that you can add into your design.

Just something to think about ...

Dan

[gp_1308]

Right, I will use FFT.  I have already generated FFT core using Xilinx CoreGen and tried few test runs.  Also planning to use  FFT block for voice activity detection as additional feature.